公开(公告)号：US20240329996A1

公开(公告)日：2024-10-03

申请号：US18579804

申请日：2022-06-22

Applicant: Arm Limited

Inventor： Alejandro Martinez Vicente ,  Nigel John Stephens ,  Jelena Milanovic

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30036

Abstract: Apparatuses, methods and programs are disclosed relating to the predication of multiple vectors in vector processing. An encoding of predicate information is disclosed which comprises an element size and an element count, wherein the predicate information comprises a multiplicity of consecutive identical predication indicators given by the element count, each predication indicator corresponding to the element size.

公开(公告)号：US11042375B2

公开(公告)日：2021-06-22

申请号：US15665781

申请日：2017-08-01

Applicant: ARM Limited

Inventor： Mbou Eyole ,  Jesse Garrett Beu ,  Alejandro Martinez Vicente ,  Timothy Hayes

IPC: G06F9/30

Abstract: An apparatus and method of operating the apparatus are provided for performing a count operation. Instruction decoder circuitry is responsive to a count instruction specifying an input data item to generate control signals to control the data processing circuitry to perform a count operation. The count operation determines a count value indicative of a number of input elements of a subset of elements in the specified input data item which have a value which matches a reference value in a reference element in a reference data item. A plurality of count operations may be performed to determine a count data item corresponding to the input data item. A register scatter storage instruction, a gather index generation instruction, and respective apparatuses responsive to them, as well as simulator implementations, are also provided.

公开(公告)号：US11132196B2

公开(公告)日：2021-09-28

申请号：US16090357

申请日：2017-04-06

Applicant: ARM Limited

Inventor： Mbou Eyole ,  Jacob Eapen ,  Alejandro Martinez Vicente

IPC: G06F9/30 ,  G06F9/34 ,  G06F9/38

Abstract: Address collisions are managed when performing vector operations. A register store stores vector operands. Execution circuitry performs memory access operations to move the vector operands between the register store and memory and data processing operations using the vector operands. The execution circuitry may iteratively execute a vector loop, where during each iteration the execution circuitry executes a sequence of instructions to implement the vector loop. The sequence includes a check instruction identifying a plurality of memory addresses. The execution circuitry responds to the check instruction to determine whether an address hazard condition exists among the plurality of memory addresses. For each iteration of the vector loop, the execution circuitry responds to the check instruction determining an absence of the hazard address condition to employ a default level of vectorization when executing the sequence of instructions to implement the vector loop. But in the presence of the address hazard condition, the execution circuitry employs a reduced level of vectorization to implement the vector loop.

公开(公告)号：US11042378B2

公开(公告)日：2021-06-22

申请号：US15743735

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Mbou Eyole ,  Alejandro Martinez Vicente

IPC: G06F9/30 ,  G06F9/32

Abstract: Data processing apparatus comprises processing circuitry to selectively apply a vector processing operation to data items at positions within data vectors according to the states of a set of respective predicate flags associated with the positions, the data vectors having a data vector processing order, each data vector comprising a plurality of data items having a data item order, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a propagation instruction to control the instruction processing circuitry to derive a set of predicate flags applicable to a current data vector in dependence upon a set of predicate flags applicable to a preceding data vector in the data vector processing order, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are inactive, all of the derived predicate flags in the set applicable to the current data vector are inactive.

公开(公告)号：US20250156184A1

公开(公告)日：2025-05-15

申请号：US18844296

申请日：2022-12-15

Applicant: Arm Limited

Inventor： Alejandro Martinez Vicente ,  Peng Sun

IPC: G06F9/30

Abstract: An apparatus has processing circuitry (16) to perform data processing, and instruction decoding circuitry (10) to control the processing circuitry to perform the data processing in response to decoding of program instructions defined according to a scalable vector instruction set architecture supporting vector instructions operating on vectors of scalable vector length to enable the same instruction sequence to be executed on apparatuses with hardware supporting different maximum vector lengths. The instruction decoding circuitry and the processing circuitry support a sub-vector-supporting instruction which treats a given vector as comprising a plurality of sub-vectors with each sub-vector comprising a plurality of vector elements. In response to the sub-vector-supporting instruction, the instruction decoding circuitry controls the processing circuitry to perform an operation for the given vector at sub-vector granularity. Each sub-vector has an equal sub-vector length.

公开(公告)号：US11314514B2

公开(公告)日：2022-04-26

申请号：US15741303

申请日：2016-06-23

Applicant: ARM Limited

Inventor： Nigel John Stephens ,  Grigorios Magklis ,  Alejandro Martinez Vicente ,  Nathanael Premillieu

IPC: G06F1/00 ,  G06F9/30

Abstract: A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. The scaling vector length querying instructions may be in the form of count instructions, increment instructions or decrement instructions. The instructions may include a pattern constraint applying a constraint, such as modulo(M) or power of 2 to the partial result value representing the number of vector elements provided for the register element size specified for the instruction.

公开(公告)号：US10678506B2

公开(公告)日：2020-06-09

申请号：US15665715

申请日：2017-08-01

Applicant: ARM Limited

Inventor： Alejandro Martinez Vicente ,  Jesse Garrett Beu ,  Mbou Eyole ,  Timothy Hayes

IPC: G06F9/30 ,  G06F7/02

Abstract: An apparatus and a method of operating the apparatus are provided for performing a comparison operation to match a given sequence of values within an input vector. Instruction decoder circuitry is responsive to a string match instruction specifying a segment of an input vector to generate control signals to control the data processing circuitry to perform a comparison operation. The comparison operation determines a comparison value indicative of whether each input element of a required set of consecutive input elements of the segment has a value which matches a respective value in consecutive reference elements of the reference data item. A plurality of comparison operations may be performed to determine a match vector corresponding to the segment of the input vector to indicate the start position of the substring in the input vector. A string match instruction, as well as simulator virtual machine implementations, are also provided.

公开(公告)号：US10430192B2

公开(公告)日：2019-10-01

申请号：US15748734

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Grigorios Magklis ,  Alejandro Martinez Vicente ,  Nathanael Premillieu ,  Mbou Eyole

IPC: G06F9/30 ,  G06F9/38

Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of a data vector comprising a plurality of data items at respective positions in the data vector, according to the state of respective predicate flags associated with the positions; the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a WHILE instruction and a CHANGE instruction, to control the instruction processing dependent upon a number of the predicate flags.