公开(公告)号：US20160064054A1

公开(公告)日：2016-03-03

申请号：US14836657

申请日：2015-08-26

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Hsin-Yu Chen ,  Sabarish Ittamveetil ,  Yew Keong Chong ,  Indranil Basu ,  Vikash

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C8/18 ,  G06F13/28 ,  G11C5/025 ,  G11C7/062 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/12

Abstract: A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal.

Abstract translation: 提供了一种操作存储器件的存储器件和方法。 存储器件包括被配置为接收存储器件的时钟信号的全局控制电路，并且存储器件配置为响应于时钟信号的单个边沿执行双存储器访问。 响应于时钟信号的单个边沿而产生用于双存储器存取的第一次访问的第一内部时钟脉冲和用于双存储器访问的第二访问的第二内部时钟脉冲。 全局控制电路根据由第一访问指示的第一组与由第二访问指示的第二组之间的比较产生比较信号，并且第二组的本地组控制电路被配置为产生第二内部时钟脉冲 依赖于比较信号。

公开(公告)号：US09627022B2

公开(公告)日：2017-04-18

申请号：US14836657

申请日：2015-08-26

Applicant: ARM Limited

Inventor： Andy Wangkun Chen ,  Hsin-Yu Chen ,  Sabarish Ittamveetil ,  Yew Keong Chong ,  Indranil Basu ,  Vikash

IPC: G11C8/18 ,  G11C5/02 ,  G11C7/22 ,  G11C7/10 ,  G11C8/12 ,  G11C7/06 ,  G06F13/28

CPC classification number: G11C8/18 ,  G06F13/28 ,  G11C5/025 ,  G11C7/062 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/12

Abstract: A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal.