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    Double Pumped Memory Techniques
    1.
    发明申请
    Double Pumped Memory Techniques 有权
    双抽液记忆技术

    公开(公告)号：US20160064054A1

    公开(公告)日：2016-03-03

    申请号：US14836657

    申请日：2015-08-26

    Applicant: ARM Limited

    Inventor： Andy Wangkun Chen ,  Hsin-Yu Chen ,  Sabarish Ittamveetil ,  Yew Keong Chong ,  Indranil Basu ,  Vikash

    IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06

    CPC classification number: G11C8/18 ,  G06F13/28 ,  G11C5/025 ,  G11C7/062 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/222 ,  G11C8/12

    Abstract: A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal.

    Abstract translation: 提供了一种操作存储器件的存储器件和方法。 存储器件包括被配置为接收存储器件的时钟信号的全局控制电路，并且存储器件配置为响应于时钟信号的单个边沿执行双存储器访问。 响应于时钟信号的单个边沿而产生用于双存储器存取的第一次访问的第一内部时钟脉冲和用于双存储器访问的第二访问的第二内部时钟脉冲。 全局控制电路根据由第一访问指示的第一组与由第二访问指示的第二组之间的比较产生比较信号，并且第二组的本地组控制电路被配置为产生第二内部时钟脉冲 依赖于比较信号。

    System Cache Peak Power Management
    5.
    发明公开
    System Cache Peak Power Management 审中-公开

    公开(公告)号：US20230154526A1

    公开(公告)日：2023-05-18

    申请号：US17530095

    申请日：2021-11-18

    Applicant: Arm Limited

    Inventor： Edward Martin McCombs, JR. ,  Hsin-Yu Chen

    IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4076

    CPC classification number: G11C11/4091 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4076

    Abstract: Various implementations described herein are related to a device having memory with sense amplifiers and precharge blocks arranged in an array with a first side and a second side. The first side has first sense amplifiers and first precharge blocks coupled together with first bitlines, and the second side has second sense amplifiers and second precharge blocks coupled together with second bitlines. The device has a first delay block coupled to the first precharge blocks in the first side of the array, and the first delay block delays precharge of the first bitlines with a first precharge burst in a multi-burst precharge event. The device has a second delay block coupled to the second precharge blocks in the second side of the array, and the second delay block delays precharge of the second bitlines with a second precharge burst in the multi-burst precharge event.

    System cache peak power management
    7.
    发明授权
    System cache peak power management 有权

    公开(公告)号：US11935580B2

    公开(公告)日：2024-03-19

    申请号：US17530095

    申请日：2021-11-18

    Applicant: Arm Limited

    Inventor： Edward Martin McCombs, Jr. ,  Hsin-Yu Chen

    IPC: G11C7/12 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094

    CPC classification number: G11C11/4091 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4094

    Abstract: One implementation described herein is related to a device having memory with sense amplifiers and precharge blocks arranged in an array with a first side and a second side. The first side has first sense amplifiers and first precharge blocks coupled together with first bitlines, and the second side has second sense amplifiers and second precharge blocks coupled together with second bitlines. The device has a first delay block coupled to the first precharge blocks in the first side of the array, and the first delay block delays precharge of the first bitlines with a first precharge burst in a multi-burst precharge event. The device has a second delay block coupled to the second precharge blocks in the second side of the array, and the second delay block delays precharge of the second bitlines with a second precharge burst in the multi-burst precharge event.

    Level shift latch circuitry
    8.
    发明授权
    Level shift latch circuitry 有权

    公开(公告)号：US11005461B2

    公开(公告)日：2021-05-11

    申请号：US16004009

    申请日：2018-06-08

    Applicant: Arm Limited

    Inventor： Andy Wangkun Chen ,  Sai Sriharsha Manapragada ,  Yicong Li ,  Yew Keong Chong ,  Bikas Maiti ,  Sanjay Mangal ,  Hsin-Yu Chen

    IPC: H03K3/356 ,  H03K17/22

    Abstract: Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.

    Level shifter with bypass
    9.
    发明授权
    Level shifter with bypass 有权

    公开(公告)号：US10535386B2

    公开(公告)日：2020-01-14

    申请号：US15603252

    申请日：2017-05-23

    Applicant: ARM Limited

    Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Rahul Mathur ,  Abhishek Baradia ,  Hsin-Yu Chen

    IPC: G11C8/06 ,  G11C8/10

    Abstract: Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.

    Memory device and method of controlling leakage current within such a memory device
    10.
    发明授权
    Memory device and method of controlling leakage current within such a memory device 有权
    存储器件和控制这种存储器件内的漏电流的方法

    公开(公告)号：US09147451B2

    公开(公告)日：2015-09-29

    申请号：US13847743

    申请日：2013-03-20

    Applicant: ARM Limited

    Inventor： Yew Keong Chong ,  Sanjay Mangal ,  Hsin-Yu Chen

    IPC: G11C11/00 ,  G11C7/18 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    CPC classification number: G11C7/18 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

    Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column group includes circuitry to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell has coupling circuitry connected between the associated read bit line and a second voltage level different to the first voltage level. During read operation the coupling circuitry associated with the activated memory cell selectively discharges the associated read bit line towards the second voltage level dependent on the data value stored within that activated memory cell. The clamping circuitry connects the associated read bit line to the second voltage level.

    Abstract translation: 存储器装置包括布置成多个行和列的存储器单元的阵列，每行耦合到相关联的读取字线，并且每列形成至少一个列组，其中每个列组的存储单元耦合到 相关的读位线。 每列组包括在读取操作之前将相关读取位线预充电到第一电压电平的电路。 每个存储单元具有连接在相关读取位线和不同于第一电压电平的第二电压电平之间的耦合电路。 在读取操作期间，与激活的存储器单元相关联的耦合电路根据存储在该激活的存储器单元内的数据值，选择性地将关联的读取位线朝向第二电压电平放电。 钳位电路将相关读取位线连接到第二电压电平。

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