公开(公告)号：US11360850B2

公开(公告)日：2022-06-14

申请号：US15073807

申请日：2016-03-18

Applicant: ARM LIMITED

Inventor： Michele Riga ,  Kauser Yakub Johar

IPC: G06F11/10 ,  H03M13/13 ,  H03M13/00 ,  H03M13/35 ,  H03M13/29 ,  G06F11/24

Abstract: An error protection key generation method and system are provided, the method being used to generate a key for use in computing an error protection code for an input data value according to a chosen error protection scheme. The method comprises inputting a plurality of desired data value sizes, and then applying a key generation algorithm to generate a key for use in computing the error protection code for a maximum data value size amongst the plurality of data value sizes. The key generation algorithm is arranged so that it generates the key so as to comprise a plurality of sub-keys, where each sub-key is associated with one of the input data value sizes, and where each sub-key conforms to a key requirement of the error protection scheme. As a result, a generic key is produced containing a plurality of sub-keys, where each sub-key is associated with a particular desired data value size, and can be extracted and used independently given that each sub-key conforms to the error protection scheme requirements. This provides significant benefits in the design and verification of error protection circuits using such keys.

公开(公告)号：US11579889B2

公开(公告)日：2023-02-14

申请号：US16950936

申请日：2020-11-18

Applicant: ARM Limited

Inventor： Jatin Bhartia ,  Kauser Yakub Johar ,  Antony John Penton

IPC: G06F9/38 ,  G06F9/30

Abstract: A processing system 2 includes a processing pipeline 12, 14, 16, 18, 28 which includes fetch circuitry 12 for fetching instructions to be executed from a memory 6, 8. Buffer control circuitry 34 is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry 16), to accumulate within one or more buffers 30, 32 fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.

公开(公告)号：US10896111B2

公开(公告)日：2021-01-19

申请号：US16670063

申请日：2019-10-31

Applicant: Arm Limited

Inventor： Mohammadi Shabbirhussain Bharmal ,  Kauser Yakub Johar ,  Francisco João Feliciano Gaspar

IPC: G06F11/30 ,  G11C5/04 ,  G11C29/10 ,  G11C29/12

Abstract: Circuitry comprises data handling circuitry having a memory, the data handling circuitry being operable in a primary mode in which the data handling circuitry performs a data handling function by accessing the memory and in a secondary mode in which the data handling circuitry performs the data handling function independently of the memory; test circuitry to control a test operation during execution of a set of data processing instructions by a data processor configured to execute data processing instructions by reference to the data handling function performed by the data handling circuitry; in which: the test circuitry is configured to control the data handling circuitry to transition from the primary mode to the secondary mode in response to initiation of a test operation on the memory so that the data processor executes one or more of the set of data processing instructions by reference to the data handling function performed by the data handling circuitry in the secondary mode at least while the test operation is performed on the memory; and the test circuitry is configured to control the data handling circuitry to return to the primary mode in response to completion of the test operation on the memory.

公开(公告)号：US11221899B2

公开(公告)日：2022-01-11

申请号：US16580045

申请日：2019-09-24

Applicant: Arm Limited

Inventor： Kauser Yakub Johar ,  Loïc Pierron

IPC: G06F9/38 ,  G06F11/07 ,  G06F13/40 ,  G06F9/52 ,  G06F13/16 ,  G06F11/16

Abstract: An apparatus is described comprising a cluster of processing elements. The cluster having a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking correctness of a primary processing workload performed by the primary processing element. Each processing element has an associated local memory comprising a plurality of memory locations. A local memory access control mechanism is configured, during the lock mode, to allow the at least one primary processing element to access memory locations within the local memory associated with the at least one redundant processing element.

公开(公告)号：US10331531B2

公开(公告)日：2019-06-25

申请号：US15447673

申请日：2017-03-02

Applicant: ARM Limited

Inventor： Balaji Venu ,  Kauser Yakub Johar ,  Marco Bonino

IPC: G06F11/07 ,  G06F11/22 ,  G06F11/24 ,  G06F11/27 ,  G06F11/273

Abstract: Apparatus and a method for processor core self-testing are disclosed. The apparatus comprises processor core circuitry to perform data processing operations by executing data processing instructions. Separate self-test control circuitry causes the processor core circuitry to temporarily switch from a first state of executing the data processing instructions to a second state of executing a self-test sequence of instructions, before returning to the first state of executing the data processing instructions without a reboot of the processor core circuitry being required. There is also self-test support circuitry, wherein the processor core circuitry is responsive to the self-test sequence of instructions to cause an export of at least one self-test data item via the self-test support circuitry to the self-test control circuitry.

公开(公告)号：US10084478B2

公开(公告)日：2018-09-25

申请号：US15587429

申请日：2017-05-05

Applicant: ARM Limited

Inventor： Kauser Yakub Johar

IPC: H03M13/00 ,  H03M13/05 ,  G06F11/10

CPC classification number: H03M13/05 ,  G06F11/1016 ,  H03M13/19 ,  H03M13/2909 ,  H03M13/616

Abstract: An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error code generation circuitry for receiving that block and a mask array comprising a plurality of mask rows, and for then applying an error code generation algorithm to generate an error code for the block. The error code comprises a plurality of check bits, where each check bit is determined using the block and a corresponding mask row of the mask array. Each mask row comprises a plurality of mask bits, each mask bit being associated with a corresponding bit of the block. At least one mask row has its mask bit values constrained so as to ensure that when all of the data bits of the block have the same value, the error code generated by the error code generation circuitry has at least one check bit having a different value to the value of the data bits irrespective of the value of the address bits. In addition to supporting detection and/or correction of errors in the data bits, such an approach also allows memory address decode errors to be detected while in addition allowing detection of stuck at zero or stuck at one errors in a memory's output.