公开(公告)号：US09767870B1

公开(公告)日：2017-09-19

申请号：US15238551

申请日：2016-08-16

Applicant: ARM Limited

Inventor： Rajiv Kumar Roy ,  Kanika Malik ,  Manoj Puthan Purayil ,  Vikash

IPC: G11C5/14 ,  G11C7/10 ,  G11C7/06 ,  G11C8/10

CPC classification number: G11C5/14 ,  G11C7/065 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/417 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include core circuitry having an array of memory cells and a row decoder that accesses each of the memory cells via a selected wordline and a wordline signal. The core circuitry may operate at a first supply voltage. The integrated circuit may include periphery circuitry having a column decoder that accesses each of the memory cells via a selected bitline. The periphery circuitry may operate at a second supply voltage that is different than the first supply voltage. The periphery circuitry may include voltage differential sensing circuitry that may compare the first supply voltage to the second supply voltage, sense a voltage differential between the first and second supply voltages, and delay the wordline signal when the voltage differential is greater than a threshold voltage.

公开(公告)号：US09583209B1

公开(公告)日：2017-02-28

申请号：US14963111

申请日：2015-12-08

Applicant: ARM Limited

Inventor： Rajiv Kumar Roy ,  Fakhruddin Ali Bohra ,  Manish Trivedi ,  Sumant Kumar Thapliyal ,  Vikash

IPC: G11C8/00 ,  G11C17/08

CPC classification number: G11C17/08 ,  G11C8/12

Abstract: Various implementations described herein are directed to an integrated circuit having high density memory architecture. The integrated circuit may include a plurality of bank arrays having multiple segments of bitcells configured to share local control. The integrated circuit may include a plurality of control lines coupling the local control to each of the multiple segments of bitcells. In some instances, during activation of a segment of bitcells by the local control via one of the control lines, another segment of bitcells may be deactivated by the local control via another of the control lines.

Abstract translation: 本文描述的各种实现涉及具有高密度存储器架构的集成电路。 集成电路可以包括具有被配置为共享本地控制的多个位单元段的多个存储体阵列。 集成电路可以包括将本地控制耦合到位单元的多个段中的每一个的多个控制线。 在一些情况下，在本地控制通过控制线之一激活位单元的段时，可以通过另一控制线的本地控制来停用另一段位单元。