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    Digitally calibrated successive approximation register analog-to-digital converter
    3.
    发明授权
    Digitally calibrated successive approximation register analog-to-digital converter 有权

    公开(公告)号：US09831887B2

    公开(公告)日：2017-11-28

    申请号：US15391573

    申请日：2016-12-27

    Applicant: Avnera Corporation

    Inventor： Jianping Wen ,  Garry Link ,  Wai Lee

    IPC: H03M1/10 ,  H03M1/38

    CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804

    Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.

    DIGITALLY CALIBRATED SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER
    4.
    发明申请
    DIGITALLY CALIBRATED SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER 有权

    公开(公告)号：US20170126240A1

    公开(公告)日：2017-05-04

    申请号：US15391573

    申请日：2016-12-27

    Applicant: Avnera Corporation

    Inventor： Jianping Wen ,  Garry Link ,  Wai Lee

    IPC: H03M1/10 ,  H03M1/38

    CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804

    Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.

    Digitally calibrated successive approximation register analog-to-digital converter
    5.
    发明授权
    Digitally calibrated successive approximation register analog-to-digital converter 有权
    数字校准的逐次逼近寄存器模数转换器

    公开(公告)号：US09531400B1

    公开(公告)日：2016-12-27

    申请号：US14932798

    申请日：2015-11-04

    Applicant: AVNERA CORPORATION

    Inventor： Jianping Wen ,  Garry Link ,  Wai Lee

    IPC: H03M1/06 ,  H03M1/40 ,  H03M1/44 ,  H03M1/46

    CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804

    Abstract: A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.

    Abstract translation: 电路可以包括具有第一输入，第二输入和输出的电压比较器Vd; 具有顶板和底板的第一多个电容器Cp [0：n]，其中每个顶板与电压比较器Vd的第一输入电耦合，其中每个顶板也可切换地电耦合到 共模电压Vcm，并且其中每个底板可切换地电耦合在第一输入电压Vinp，参考电压Vref，共模电压Vcm和地之间; 分别具有顶板和底板的第二多个电容器Cn [0：n]，其中每个顶板与电压比较器Vd的第二输入电耦合，其中每个顶板也可切换地电耦合到 共模电压Vcm，并且其中每个底板可切换地电耦合在第二输入电压Vinn，参考电压Vref，共模电压Vcm和地之间; 以及与电压比较器Vd的输出耦合的逐次逼近寄存器（SAR）控制器。

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