公开(公告)号：US10560114B2

公开(公告)日：2020-02-11

申请号：US16174088

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US20190043469A1

公开(公告)日：2019-02-07

申请号：US16154526

申请日：2018-10-08

Applicant: Avnera Corporation

Inventor： Amit Kumar ,  Wai Lang Lee ,  Jianping Wen

IPC: G10K11/178

Abstract: A method of adaptive noise cancellation can include receiving an audio input signal, receiving an ambient signal through a microphone, modifying filter parameters of a noise filter based on the ambient signal, and filtering the audio input signal based on the modified filter parameters.

公开(公告)号：US10148280B2

公开(公告)日：2018-12-04

申请号：US15853779

申请日：2017-12-23

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/38 ,  H03M1/46 ,  H03M1/44 ,  H03M1/10 ,  H03M1/18

Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

公开(公告)号：US20180183455A1

公开(公告)日：2018-06-28

申请号：US15849220

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link ,  Jian Li

IPC: H03M1/46 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/462 ,  H03M1/0863 ,  H03M1/1019 ,  H03M1/1061 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/129 ,  H03M1/466 ,  H03M1/468

Abstract: The disclosure includes an analog to digital converter (ADC). The ADC includes a successive approximation register (SAR) unit including one or more capacitive networks. The capacitive networks take a sample of an analog signal. The SAR also includes a comparator to approximate digital values based on the analog signal sample via successive comparison. The ADC includes a preamplifier coupled to the SAR unit. The preamplifier amplifies the analog signal for application to the capacitive networks for sampling. The ADC also includes a rough buffer coupled to the SAR unit. The rough buffer pre-charges the capacitive networks of the SAR unit prior to application of the analog signal from the preamplifier.

公开(公告)号：US20180152196A1

公开(公告)日：2018-05-31

申请号：US15799812

申请日：2017-10-31

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Garry Link ,  Wai Laing Lee

IPC: H03M1/10 ,  H03M1/38

CPC classification number: H03M1/1009 ,  H03M1/0682 ,  H03M1/0692 ,  H03M1/38 ,  H03M1/403 ,  H03M1/462 ,  H03M1/468 ,  H03M1/804

Abstract: A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.

公开(公告)号：US10581445B2

公开(公告)日：2020-03-03

申请号：US16159498

申请日：2018-10-12

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Garry Link ,  Wai Laing Lee

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/40 ,  H03M1/46 ,  H03M1/38 ,  H03M1/80

Abstract: A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.

公开(公告)号：US20190173484A1

公开(公告)日：2019-06-06

申请号：US16174118

申请日：2018-10-29

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/44 ,  H03M1/08 ,  H03M1/06

Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

公开(公告)号：US10224952B2

公开(公告)日：2019-03-05

申请号：US15490759

申请日：2017-04-18

Applicant: Avnera Corporation

Inventor： Jianping Wen ,  Ali Hadiashar ,  Eric King ,  David Entrikin ,  Wai Lang Lee

IPC: H03M3/00

Abstract: Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

公开(公告)号：US10158373B2

公开(公告)日：2018-12-18

申请号：US15849234

申请日：2017-12-20

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/08 ,  H03M1/44 ,  H03M1/06

Abstract: The disclosure includes a mechanism for mitigating charge related disturbances in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by providing a fine reference connection and a rough reference connection. A switch array is activated to couple a current bit capacitor of a capacitor array to the rough reference connection while a current bit corresponding to the current bit capacitor is determined by a comparator. The switch array is further activated to couple a previous bit capacitor of the capacitor array to the fine reference connection while the current bit capacitor is coupled to the rough reference connection. This separates charge flow on the rough reference connection from capacitors coupled to the fine reference connection.

公开(公告)号：US20180183458A1

公开(公告)日：2018-06-28

申请号：US15853779

申请日：2017-12-23

Applicant: Avnera Corporation

Inventor： Wai Lee ,  Jianping Wen ,  Garry N. Link

IPC: H03M1/46 ,  H03M1/10 ,  H03M1/44

CPC classification number: H03M1/462 ,  H03M1/1033 ,  H03M1/188 ,  H03M1/447 ,  H03M1/468

Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.