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    DIGITALLY ENHANCED DIGITAL-TO-ANALOG CONVERTER RESOLUTION
    2.
    发明公开
    DIGITALLY ENHANCED DIGITAL-TO-ANALOG CONVERTER RESOLUTION 审中-公开

    公开(公告)号：US20230412187A1

    公开(公告)日：2023-12-21

    申请号：US18031188

    申请日：2021-10-29

    申请人： Ciena Corporation

    发明人： Mohammad Honarparvar ,  Sadok Aouini ,  Jerry Yee-Tung Lam ,  Soheyl Ziabakhsh Shalmani ,  Naim Ben-Hamida

    IPC分类号： H03M1/66 ,  H03M1/20 ,  H03M1/06

    CPC分类号： H03M1/661 ,  H03M1/0607 ,  H03M1/0682 ,  H03M1/20

    摘要： Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.

    HIGH SPEED ILLUMINATION DRIVER FOR TOF APPLICATIONS
    5.
    发明申请
    HIGH SPEED ILLUMINATION DRIVER FOR TOF APPLICATIONS 审中-公开
    用于TOF应用的高速照明驱动器

    公开(公告)号：US20160341819A1

    公开(公告)日：2016-11-24

    申请号：US14856205

    申请日：2015-09-16

    申请人： Texas Instruments Incorporated

    发明人： Jagannathan VENKATARAMAN

    IPC分类号： G01S7/497 ,  G01S7/484 ,  G06T7/00 ,  G01S7/48

    CPC分类号： G01S7/484 ,  G01S17/89 ,  H03M1/0682 ,  H03M3/358 ,  H03M3/50 ,  H03M3/502

    摘要： The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.

    摘要翻译： 本公开提供一种电路。 该电路包括放大器和数模转换器（DAC）。 放大器在放大器的输入节点处接收参考电压。 DAC通过刷新开关耦合到放大器。 DAC包括一个或多个电流元件。 一个或多个电流元件的每个电流元件接收时钟。 DAC包括一个或多个对应于一个或多个电流元件的开关。 反馈开关耦合在一个或多个开关和放大器的反馈节点之间。 DAC在放大器的反馈节点提供反馈电压。

    Analog-digital converter
    7.
    发明授权
    Analog-digital converter 有权
    模数转换器

    公开(公告)号：US08947288B2

    公开(公告)日：2015-02-03

    申请号：US13550092

    申请日：2012-07-16

    申请人： Lukas Kull

    发明人： Lukas Kull

    IPC分类号： H03M1/12 ,  H03M1/06 ,  H03M1/46

    CPC分类号： H03M1/0682 ,  H03M1/466

    摘要： A differential analog-digital converter is provided. The converter comprises a decision unit for evaluating a potential difference between two input signal lines, a number of charging units for each input signal line each configured to add a predetermined charge onto the respective input signal line, a number of discharging units for each input signal line each configured to remove a predetermined charge from the respective input signal line and a control unit for selectively switching each of the charging units and discharging units so that depending on one result of evaluating the potential difference between the two input signal lines one of the input signal lines is charged by adding the predetermined charge of the respective switched charging unit while the respective other of the input signal lines is discharged by removing the predetermined charge of the respective switched discharging unit.

    摘要翻译： 提供差分模数转换器。 转换器包括用于评估两个输入信号线之间的电位差的判定单元，每个输入信号线的充电单元的数量，每个输入信号线被配置为在各个输入信号线上添加预定的电荷，每个输入信号的放电单元数 每个配置用于从相应的输入信号线去除预定的电荷;以及控制单元，用于选择性地切换每个充电单元和放电单元，使得根据评估两个输入信号线之间的电位差的一个结果，输入 通过添加相应的切换充电单元的预定电荷来对信号线进行充电，同时通过去除各个开关放电单元的预定电荷来排出各个输入信号线。

    SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD OF OPERATING BUILT-IN SELF-TEST DEVICE FOR TESTING THE CONVERTER
    8.
    发明申请
    SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD OF OPERATING BUILT-IN SELF-TEST DEVICE FOR TESTING THE CONVERTER 有权
    成功的近似寄存器模拟数字转换器和操作内置自检器件的测试转换器的方法

    公开(公告)号：US20150029048A1

    公开(公告)日：2015-01-29

    申请号：US14178187

    申请日：2014-02-11

    申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    发明人： Young-deuk Jeon

    IPC分类号： H03M1/10 ,  H03M1/12

    CPC分类号： H03M1/1071 ,  H03M1/00 ,  H03M1/0682 ,  H03M1/1023 ,  H03M1/468

    摘要： Provided is a successive approximation register analog-to-digital converter (SAR ADC) including a digital-to-analog converter (DAC) generating and outputting first and second level voltages based on first and second analog input signals and a reference voltage signal; a comparator comparing the first and second level voltages and outputting a comparison signal according to a comparison result; and an SAR logic generating a digital signal based on the comparison signal, wherein the DAC includes: first and second input switches controlling reception of the first and second analog input signals, respectively; a first discharge switch connected electrically to the first input switch, the first discharge switch discharging leakage current according to an operation of the first input switch; and a second discharge switch connected electrically to the second input switch, the second discharge switch discharging leakage current according to an operation of the second input switch.

    摘要翻译： 提供了包括基于第一和第二模拟输入信号和参考电压信号产生并输出第一和第二电平电压的数模转换器（DAC）的逐次逼近寄存器模拟 - 数字转换器（SAR ADC） 比较器，比较第一和第二电平电压，并根据比较结果输出比较信号; 以及基于所述比较信号产生数字信号的SAR逻辑，其中所述DAC包括：分别控制所述第一和第二模拟输入信号的接收的第一和第二输入开关; 与第一输入开关电连接的第一放电开关，第一放电开关根据第一输入开关的操作放电泄漏电流; 以及与第二输入开关电连接的第二放电开关，第二放电开关根据第二输入开关的操作来放电泄漏电流。

    Successive approximation register analog-to-digital converter and method of operating built-in self-test device for testing the converter
    9.
    发明授权
    Successive approximation register analog-to-digital converter and method of operating built-in self-test device for testing the converter 有权
    逐次逼近寄存器模数转换器和操作内置自检器件的测试方法

    公开(公告)号：US08933830B1

    公开(公告)日：2015-01-13

    申请号：US14178187

    申请日：2014-02-11

    申请人： Electronics and Telecommunications Research Institute

    发明人： Young-deuk Jeon

    IPC分类号： H03M1/00 ,  H03M1/10 ,  H03M1/12

    CPC分类号： H03M1/1071 ,  H03M1/00 ,  H03M1/0682 ,  H03M1/1023 ,  H03M1/468

    摘要： Provided is a successive approximation register analog-to-digital converter (SAR ADC) including a digital-to-analog converter (DAC) generating and outputting first and second level voltages based on first and second analog input signals and a reference voltage signal; a comparator comparing the first and second level voltages and outputting a comparison signal according to a comparison result; and an SAR logic generating a digital signal based on the comparison signal, wherein the DAC includes: first and second input switches controlling reception of the first and second analog input signals, respectively; a first discharge switch connected electrically to the first input switch, the first discharge switch discharging leakage current according to an operation of the first input switch; and a second discharge switch connected electrically to the second input switch, the second discharge switch discharging leakage current according to an operation of the second input switch.

    摘要翻译： 提供了包括基于第一和第二模拟输入信号和参考电压信号产生并输出第一和第二电平电压的数模转换器（DAC）的逐次逼近寄存器模拟 - 数字转换器（SAR ADC） 比较器，比较第一和第二电平电压，并根据比较结果输出比较信号; 以及基于所述比较信号产生数字信号的SAR逻辑，其中所述DAC包括：分别控制所述第一和第二模拟输入信号的接收的第一和第二输入开关; 与第一输入开关电连接的第一放电开关，第一放电开关根据第一输入开关的操作放电泄漏电流; 以及与第二输入开关电连接的第二放电开关，第二放电开关根据第二输入开关的操作来放电泄漏电流。