摘要:
A receiver for processing a VSB modulated signal containing terrestrial broadcast high definition television information includes an input analog-to-digital converter (19) for producing a digital datastream. A symbol timing recovery and segment sync recovery network (24; FIG. 3, 4) develops a properly timed sampling clock for the digital converter (19). The symbol timing recovery network (310) responds to an output from the segment sync recovery network (328), which in turn responds to an equalized signal from an adaptive channel equalizer (34). A controlled oscillator (336) generates the sampling clock for the digital converter. A control network (340, 344, 348; FIG. 3) shifts the frequency range of the oscillator to maintain desired linear operation to enhance symbol timing acquisition.
摘要:
A digital data stream comprises alternating groups of information blocks and groups of parity blocks, each group of information blocks includes multiple information blocks and each group of parity blocks includes multiple parity blocks. An apparatus for receiving a digital data stream comprises a demodulator that receives and demodulates a digital data stream. An equalizer compensates for distortions in the digital data stream. A delay buffer generates a first stream of digital data representing the compensated digital data stream and a second stream of digital data representing a delayed version of the compensated digital data stream. A forward error correction block receives and processes the first and second streams of digital data from the delay buffer, and outputs an error corrected stream of digital data. A transport block receives and processes the error corrected stream from the forward error correction block for display.
摘要:
Channel acquisition in a digital television signal receiver is improved by determining the carrier tracking loop frequency offsets and the symbol timing recovery offsets for each channel in the television receiver. Offsets are stored in respective EEPROMs for each channel. When a channel is to be acquired in the TV receiver the tune command will be applied to the appropriate EEPROMs and the respective values are conveyed to the VSB demodulator to start acquisition of the channel.
摘要:
The determination of the signal modulation format for a channel is an important aspect of the operation of a signal receiver. A method (700) is described including the steps of receiving (710) a signal, comparing (720) a sample of the received signal to a first threshold value and a second threshold value, creating (720) a signal profile based on the comparison, and selecting (750) a modulation format for the received signal based on the signal profile. An apparatus (500) is also described including a ring counter (510) that receives a sample of an input signal, compares the sample to a first threshold value and a second threshold value, and creates a signal profile for the input signal, a signal profiler (550) that compares the signal profile for the input signal to at least two reference profiles, and a detector (560) that determines a modulation format for the input signal based on the comparison in the signal profiler (550).
摘要:
The present application generally relates to apparatuses such as television signal processing apparatus that process radio frequency signals. More specifically, the present application is particularly useful in integrated circuits that must receive a radio frequency signal and simultaneously use circuitry where the timing of the operations are based on the received RF signal and circuitry where the timing is based on a fixed rate signal with sensitivity to clock jitter. According to an exemplary embodiment, the apparatus comprises, a first input (RefClk), a second input (PllClk), an output (CLK 1X), a delay means (405, 410, 415, 420, 425), and a logic means (430, 435, 440, 445, 450, 455, 460, 465, and 470) to compare a plurality of stages of said delay means to produce an signal at said output.
摘要:
The present application generally relates to apparatuses such as television signal processing apparatus that process radio frequency signals. More specifically, the present application is particularly useful in integrated circuits that must receive a radio frequency signal and simultaneously use circuitry where the timing of the operations are based on the received RF signal and circuitry where the timing is based on a fixed rate signal with sensitivity to clock jitter. According to an exemplary embodiment, the apparatus comprises, a first input (RefClk), a second input (PllClk), an output (CLK 1X), a delay means (405, 410, 415, 420, 425), and a logic means (430, 435, 440, 445, 450, 455, 460, 465, and 470) to compare a plurality of stages of said delay means to produce an signal at said output.
摘要:
In a receiver for processing a vestigial sideband modulated signal containing terrestrial broadcast high definition television information and a pilot component, and for which multipath interference can lead to significant attenuation within narrow bands of the received signal spectrum containing the pilot tone of an Advanced Television Systems Committee high definition television broadcast signal, it has been found desirable to amplify the input signal in order to achieve synchronization of the receiver's phase-locked loop to the received pilot tone. Once this initial acquisition has been established, the amplification applied to the received signal can be reduced to a level appropriate for remaining blocks in the demodulation chain without upsetting the pilot tone synchronization. Thus, according to the present invention, the gain applied to the received ATSC VSB signal is set higher during pilot tone acquisition than it is during the remaining stages of demodulation.
摘要:
In a receiver for processing a VSB modulated signal containing terrestrial broadcast high definition television information including data packets, the received signal is converted to a digital signal (19), demodulated (22) and equalized by an adaptive channel equalizer (34). An equalized signal is processed by decoding networks including a Reed-Solomon FEC error detecting and correcting network (44). The equalizer filter coefficient step size is dynamically adjusted during the adaption process as a function of the packet error rate. A local microcontroller (60) monitors the packet error rate at the Reed-Solomon error detector and instructs the equalizer to adjust the coefficient step size in a direction to reduce the packet error rate.
摘要:
The determination of the signal modulation format for a channel is an important aspect of the operation of a signal receiver. A method (700) is described including the steps of receiving (710) a signal, comparing (720) a sample of the received signal to a first threshold value and a second threshold value, creating (720) a signal profile based on the comparison, and selecting (750) a modulation format for the received signal based on the signal profile. An apparatus (500) is also described including a ring counter (510) that receives a sample of an input signal, compares the sample to a first threshold value and a second threshold value, and creates a signal profile for the input signal, a signal profiler (550) that compares the signal profile for the input signal to at least two reference profiles, and a detector (560) that determines a modulation format for the input signal based on the comparison in the signal profiler (550).
摘要:
A software packet error system for a High Definition Television (HDTV) receiver. A data packet error signal is transferred from a forward error correcting Reed-Solomon decoder to a transport processor. In response to a segment sync signal, the transport processor generates an error signal which appears on a programmable output pin. The software packet error signal is synchronized with the outgoing data packet signal such that each data packet is bracketed or framed by its associating packet error signal. Precession of the start of the data packets forwarded on the transport but relative to the start of the data packets appearing at the output of the decoder occurs as a result of a training packet generated for every 312 data packets. The precession is reset at the beginning of every field and is predictable across the field duration with sufficient accuracy to make the software packet error mechanism feasible.