公开(公告)号：US5228065A

公开(公告)日：1993-07-13

申请号：US776152

申请日：1991-10-15

申请人： Achim Herzberger

发明人： Achim Herzberger

IPC分类号： H04J3/00 ,  H04J3/06 ,  H04L7/08 ,  H04Q11/04

CPC分类号： H04J3/0608 ,  H04J2203/0089

摘要： A synchronizing pulse is produced upon detection of a frame codeword or frame-structured binary signal consisting of a first word repeated a plurality of times and at least one second word. A demultiplexer divides the incoming signal into n words which are advanced in parallel through n shift registers of a first memory matrix, followed by the next n words, and so on. A decoder determines whether the first word is stored in each register, and increments a respective one of n counters when the word is found. An addressing logic transforms the output into a binary number which controls a multiplexer which, in turn controls arrangement of bits in a second memory matrix. A synchronizing pulse is produced when the second memory matrix contains predetermined bits of the first and second word.

摘要翻译： 在检测到由多个重复的第一个字和至少一个第二个字组成的帧码字或帧结构的二进制信号时产生同步脉冲。 多路分解器将输入信号划分成n个字，其通过第一存储器矩阵的n个移位寄存器并行地前进，随后是下一个n个字，等等。 解码器确定第一个字是否存储在每个寄存器中，并且在找到该字时递增n个计数器中的相应一个。 寻址逻辑将输出转换成控制多路复用器的二进制数，该多路复用器又控制第二存储器矩阵中的位的排列。 当第二存储器矩阵包含第一和第二字的预定位时，产生同步脉冲。

公开(公告)号：US5276689A

公开(公告)日：1994-01-04

申请号：US783294

申请日：1991-10-28

申请人： Achim Herzberger ,  Paul Presslein

发明人： Achim Herzberger ,  Paul Presslein

IPC分类号： H04J3/04 ,  H04J3/06 ,  H04L5/22

CPC分类号： H04J3/047 ,  H04J3/0623

摘要： A demultiplexer for an isochronous multiplex signal is described which signal consists of isochronous sub-signals interleaved block by block. The demultiplexer comprises a read-write memory (MXA, MXB, MXC, MXD) as well as a read-write control (ST). The proposed circuit arrangement may be devised in a highly advantageous manner as an integrated circuit because it is has been considered that, for example, the manufacturers of gate arrays leave the user only the choice of using building blocks depicted in a catalogue. These building blocks constitute the function blocks (MXA to MXD) which are provided for partitioning an STM-16 signal into four sub-signals (STM4A, STM4B, STM4C, STM4D). The control signals for these function blocks (TL15:0, Z(3:0), T311, T622) are produced by a control circuit (ST) whose central module is a four-stage cyclic counter. The necessary control signals are derived from the count of the cyclic counter by means of addressable demultiplexers.

摘要翻译： 描述了用于等时多路复用信号的解复用器，哪个信号由逐个块交错的同步子信号组成。 解复用器包括读写存储器（MXA，MXB，MXC，MXD）以及读写控制（ST）。 所提出的电路装置可以作为集成电路以非常有利的方式设计，因为已经认为例如门阵列的制造商仅仅使用户使用目录中描绘的构建块的选择。 这些构建块构成功能块（MXA至MXD），用于将STM-16信号分为四个子信号（STM4A，STM4B，STM4C，STM4D）。 这些功能块（TL15：0，Z（3：0），T311，T622）的控制信号由其中央模块是四级循环计数器的控制电路（ST）产生。 通过可寻址解复用器从循环计数器的计数中导出必要的控制信号。

公开(公告)号：US07184475B2

公开(公告)日：2007-02-27

申请号：US10054551

申请日：2002-01-22

申请人： Ralf Dohmen ,  Christoph Schulien ,  Herbert Haunstein ,  Achim Herzberger ,  Georg Roell ,  Konrad Sticht

发明人： Ralf Dohmen ,  Christoph Schulien ,  Herbert Haunstein ,  Achim Herzberger ,  Georg Roell ,  Konrad Sticht

IPC分类号： H03H7/30 ,  H03K5/159 ,  G06F17/10 ,  H04B3/14

CPC分类号： H04L25/03038 ,  H04L1/0045 ,  H04L25/063 ,  H04L2025/03617

摘要： A method of adjusting equalization parameters in a receiver wherein a bit error rate (BER) in a data stream is measured from the number of corrected bits in data blocks which have an information section and an error correction section. A predetermined equalization parameter is changed, and the bit error rate (BER) after change is again measured to find out how to change the predetermined equalization parameter until an optimum is reached.When adjusting the threshold value of the receiver, the history of occurring bits preceding the actual sampled bit is taken into consideration in that the amount and direction of adjustment is derived from a look-up table.

摘要翻译： 一种在接收机中调整均衡参数的方法，其中根据具有信息部分和纠错部分的数据块中的校正比特数来测量数据流中的误码率（BER）。 改变预定的均衡参数，并且再次测量改变之后的误码率（BER），以找出如何改变预定的均衡参数，直到达到最佳值。 当调整接收机的阈值时，考虑到实际采样位之前出现位的历史，因为从查找表导出调整的量和方向。

公开(公告)号：US5177742A

公开(公告)日：1993-01-05

申请号：US759696

申请日：1991-09-09

申请人： Achim Herzberger

发明人： Achim Herzberger

IPC分类号： H04J3/04 ,  H04J3/16

CPC分类号： H04J3/047 ,  H04J3/1611

摘要： The described demultiplexer is intended for a serial and isochronous multiplex signal consisting of Q isochronous tributary signals interleaved bock-by-block, each block containing K bits. An associated multiplexer is also described. In order to keep the required memory capacity in a demultiplexer as small as possible, a write/read memory (5) is utilized, into which the bits of the multiplex signal are cyclically written and from which, simultaneously, the bits of the tributary signals are read out cyclically. A write/read control (4) coordinates the writing and reading processes in a manner such that no collisions occur. In an exemplary embodiment the bits of the multiplex signal are written into the write/read memory (5) bit-by-bit by means of a serial-to-parallel converter (2). Reading is effected bit-by-bit while utilizing read logics (81, 82, 83, 84) which are also controlled by the write/read control (4) via addresses. At the output (91, 92, 93, 94) of each of these read logics (81, 82, 83, 84) the tributary signals are available in a serial form.

摘要翻译： 所描述的解复用器旨在用于由逐个块交织的Q个等时支路信号组成的串行和同步多路复用信号，每个块包含K个比特。 还描述了相关联的多路复用器。 为了尽可能地将解复用器中的所需存储容量保持在尽可能小的位置，使用写入/读取存储器（5），多路复用信号的比特被循环写入到该存储器中，同时从该寄存器 被循环读出。 写入/读取控制（4）以不发生冲突的方式来协调写入和读取过程。 在示例性实施例中，多路复用信号的位通过串并转换器（2）逐位地写入写/读存储器（5）。 同时利用读写逻辑（81,82,83,84）进行逐位读取，读逻辑也通过地址由写/读控制（4）控制。 在这些读取逻辑（81,82,83,84）中的每一个的输出（91,92,93,94）上，支路信号以串行形式可用。