公开(公告)号：US20150318056A1

公开(公告)日：2015-11-05

申请号：US14266039

申请日：2014-04-30

Applicant: Advanced Micro Devices Inc.

Inventor： Amlan Ghosh ,  Keith Allen Kasprak ,  John Wuu ,  John Reginald Riley, III

IPC: G11C29/02 ,  G11C11/419

CPC classification number: G11C29/02 ,  G11C11/41 ,  G11C11/419 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5006

Abstract: A test circuit for a static random access memory (SRAM) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. Subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on the complementary bit line of another one of the plurality of stages. The test circuit also includes inversion logic deployed between two of the plurality of stages.

Abstract translation: 用于静态随机存取存储器（SRAM）阵列的测试电路包括以环形耦合的多个级。 每个级包括多个比特单元，用于存储耦合到多个比特单元的信息，位线和互补位线以及耦合到多个比特单元的多个字线。 基于在多个级中的另一个级的互补位线上断言的信号来选择性地使能多级级中的每一级的多个字线的子集。 测试电路还包括部署在多个级中的两个级之间的反相逻辑。

公开(公告)号：US10438636B2

公开(公告)日：2019-10-08

申请号：US15834644

申请日：2017-12-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Tawfik Ahmed ,  Amlan Ghosh ,  Keith A. Kasprak ,  Ricardo Cantu

IPC: G11C7/12 ,  H01L23/522 ,  G11C7/10 ,  G11C5/06

Abstract: Write assist circuitry facilitates increased voltage applied to a memory device such as a memory cell or bitcell in changing a logical state of the memory device during a write operation. The write assist circuitry includes a second capacitive line or “metal cap” in addition to a first capacitive line coupled to one of a pair of bitlines to which voltage may be selectively applied. The capacitive lines provide increased write assistance to the memory device. The second capacitive line structurally lies in a second orientation and is formed in an integrated circuit second metal layer relative to the first capacitive line in some embodiments. The additional capacitive line provides negative bitline assistance by selectively driving its corresponding bitlines to be negative during a write operation.

公开(公告)号：US09373418B2

公开(公告)日：2016-06-21

申请号：US14146118

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Stephen Kosonocky ,  Amlan Ghosh

IPC: G11C29/00 ,  G11C29/24 ,  G11C29/02 ,  G11C11/41 ,  G11C29/04 ,  G11C29/12

CPC classification number: G11C29/24 ,  G11C11/41 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/1204

Abstract: A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a plurality of word lines, a plurality of bit line pairs, and memory cells located at intersections of the plurality of word lines and the plurality of bit line pairs. The memory cells are of a same type as memory cells in the memory array. The built-in self test circuit is coupled to the replica array for adding a capacitance to at least one bit line of the plurality of bit line pairs, for sensing a read time of memory cells of the replica array with the capacitance so added, and for providing a headroom signal in response to the read time.

Abstract translation: 具有净空监测的电路包括具有存储单元的存储器阵列，复制阵列和内置自测电路。 复制数组具有多个字线，多个位线对和位于多个字线和多个位线对的交点处的存储单元。 存储单元与存储器阵列中的存储单元具有相同的类型。 内置的自检电路耦合到副本阵列，用于向多个位线对中的至少一个位线添加电容，用于利用所添加的电容感测副本阵列的存储器单元的读取时间;以及 用于响应于读取时间提供净空信号。

公开(公告)号：US20150187437A1

公开(公告)日：2015-07-02

申请号：US14146118

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Stephen Kosonocky ,  Amlan Ghosh

IPC: G11C29/12 ,  G11C29/44

CPC classification number: G11C29/24 ,  G11C11/41 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/1204

Abstract: A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a plurality of word lines, a plurality of bit line pairs, and memory cells located at intersections of the plurality of word lines and the plurality of bit line pairs. The memory cells are of a same type as memory cells in the memory array. The built-in self test circuit is coupled to the replica array for adding a capacitance to at least one bit line of the plurality of bit line pairs, for sensing a read time of memory cells of the replica array with the capacitance so added, and for providing a headroom signal in response to the read time.

Abstract translation: 具有净空监测的电路包括具有存储单元的存储器阵列，复制阵列和内置自测电路。 复制数组具有多个字线，多个位线对和位于多个字线和多个位线对的交点处的存储单元。 存储单元与存储器阵列中的存储单元具有相同的类型。 内置的自检电路耦合到副本阵列，用于向多个位线对中的至少一个位线添加电容，用于利用所添加的电容感测副本阵列的存储器单元的读取时间;以及 用于响应于读取时间提供净空信号。

公开(公告)号：US09355743B2

公开(公告)日：2016-05-31

申请号：US14266039

申请日：2014-04-30

Applicant: Advanced Micro Devices Inc.

Inventor： Amlan Ghosh ,  Keith Allen Kasprak ,  John Wuu ,  John Reginald Riley, III

IPC: G11C29/02 ,  G11C11/419

CPC classification number: G11C29/02 ,  G11C11/41 ,  G11C11/419 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5006

Abstract: A test circuit for a static random access memory (SRAM) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. Subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on the complementary bit line of another one of the plurality of stages. The test circuit also includes inversion logic deployed between two of the plurality of stages.

Abstract translation: 用于静态随机存取存储器（SRAM）阵列的测试电路包括以环形耦合的多个级。 每个级包括多个比特单元，用于存储耦合到多个比特单元的信息，位线和互补位线以及耦合到多个比特单元的多个字线。 基于在多个级中的另一个级的互补位线上断言的信号来选择性地使能多级级中的每一级的多个字线的子集。 测试电路还包括部署在多个级中的两个级之间的反相逻辑。