公开(公告)号：US20250112047A1

公开(公告)日：2025-04-03

申请号：US18478746

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Chandra Sekhar Mandalapu ,  Raja Swaminathan ,  Liwei Wang ,  John Wuu

IPC: H01L21/20 ,  H01L21/683 ,  H01L23/00

Abstract: A hybrid bonding method includes fabricating plural semiconductor devices in a region of a bottom wafer adjacent to a front surface thereof, fusion bonding the front surface to a carrier substrate, thinning the bottom wafer opposite to the front surface to expose conductive regions of the semiconductor devices, forming a dielectric layer over a backside of the semiconductor devices, forming openings in the dielectric layer to expose the conductive regions, forming metal pads within the openings, dicing the bottom wafer and the carrier substrate to singulate the plural semiconductor devices, bonding the dielectric layer overlying the backside of the semiconductor devices to a dielectric layer overlying a front surface of a top wafer, bonding the metal pads within the openings in the dielectric layer to metal pads overlying the front surface of the top wafer, and removing the carrier substrate from the front surface of the bottom wafer.

公开(公告)号：US20240038596A1

公开(公告)日：2024-02-01

申请号：US17873591

申请日：2022-07-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Chandra Sekhar Mandalapu ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Richard T. Schultz

IPC: H01L21/84 ,  H01L21/02 ,  H01L23/14 ,  H01L23/498 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/02164 ,  H01L23/147 ,  H01L23/49827 ,  H01L27/1203

Abstract: An apparatus and method for efficiently increasing semiconductor chip functionality in a particular area. A semiconductor fabrication process (or process) grows a silicon substrate layer, and forms multiple p-type and n-type transistors along a front side surface of the silicon substrate layer. The process flips the silicon substrate layer and removes silicon substrate leaving a particular thickness of the silicon substrate layer. The process forms multiple p-type and n-type transistors along the back side surface of the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the back side surface to particular signals. The process forms through silicon vias (TSVs) that traverse through the silicon substrate layer. The process again flips the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the front side surface to particular signals.