公开(公告)号：US12107075B2

公开(公告)日：2024-10-01

申请号：US18324744

申请日：2023-05-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lei Fu ,  Brett P. Wilkerson ,  Rahul Agarwal

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5381 ,  H01L23/5389 ,  H01L24/13 ,  H01L2225/06541

Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.

公开(公告)号：US11709327B2

公开(公告)日：2023-07-25

申请号：US17361033

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brett P. Wilkerson ,  Raja Swaminathan ,  Kong Toon Ng ,  Rahul Agarwal

IPC: G02B6/42 ,  G02B6/43

CPC classification number: G02B6/4274 ,  G02B6/425 ,  G02B6/4255 ,  G02B6/43

Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.

公开(公告)号：US20230207544A1

公开(公告)日：2023-06-29

申请号：US17560691

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Rahul Agarwal ,  Raja Swaminathan ,  Brett P. Wilkerson

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/18 ,  H01L24/16 ,  H01L25/50 ,  H01L21/76898 ,  H01L2224/16145 ,  H01L2224/16225

Abstract: A semiconductor device includes one or more active devices disposed between a processor die and a package substrate. The semiconductor device includes a first layer with a processor die, a second layer with one or more active devices, and a third layer with a package substrate, where the second layer is disposed between the first and third layers. The one or more active devices are semiconductor-based devices, such as voltage regulators, that participate in supplying power to the processor die and are electrically connected to the processor die using various connection configurations. The implementations use short path lengths for improved performance with a compact structure that avoids the use of edge wiring or interposers without occupying processor die space. Implementations include the use of through-silicon vias (TSVs) to provide short path lengths while reducing the number of connection resources used by the one or more power components.

公开(公告)号：US20220392882A1

公开(公告)日：2022-12-08

申请号：US17891444

申请日：2022-08-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Brett P. Wilkerson ,  Milind S. Bhagavat ,  Rahul Agarwal ,  Dmitri Yudanov

IPC: H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48

Abstract: A three-dimensional integrated circuit includes a first die structure having a first geometry. The first die structure includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The three-dimensional integrated circuit includes a second die structure having a second geometry. A stacked portion of the second die structure is aligned with the first region. The three-dimensional integrated circuit includes an additional die structure stacked with the first die structure and the second die structure. The additional die structure has the first geometry or the second geometry.

公开(公告)号：US11018125B2

公开(公告)日：2021-05-25

申请号：US16927111

申请日：2020-07-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00 ,  H01L23/433

Abstract: Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

公开(公告)号：US20200185367A1

公开(公告)日：2020-06-11

申请号：US16215969

申请日：2018-12-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L49/02 ,  H01L21/48 ,  H01L21/56

Abstract: In at least one embodiment, an integrated circuit product includes a redistribution layer, an integrated circuit die disposed above the redistribution layer, and a discrete device disposed laterally with respect to the integrated circuit die and disposed above the redistribution layer. The integrated circuit product may include encapsulant mechanically coupling the redistribution layer, the integrated circuit die, and the discrete device. The integrated circuit product may include first conductive vias through the redistribution layer and second conductive vias through the redistribution layer. The first conductive vias may be electrically coupled to the integrated circuit die and the second conductive vias being electrically coupled to the discrete device. The discrete device may include a discrete capacitor device made from a ceramic material, electrolytic materials, or electrochemical materials.

公开(公告)号：US20200168549A1

公开(公告)日：2020-05-28

申请号：US16778815

申请日：2020-01-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind S. Bhagavat ,  Rahul Agarwal

IPC: H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L23/522 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

公开(公告)号：US20200066677A1

公开(公告)日：2020-02-27

申请号：US16110678

申请日：2018-08-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Milind Bhagavat ,  David Hugh McIntyre ,  Rahul Agarwal

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A data processor is implemented as an integrated circuit. The data processor includes a processor die. The processor die is connected to an integrated voltage regulator die using die-to-die bonding. The integrated voltage regulator die provides a regulated voltage to the processor die, and the processor die operates in response to the regulated voltage.

公开(公告)号：US12183675B2

公开(公告)日：2024-12-31

申请号：US16351728

申请日：2019-03-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rahul Agarwal ,  Chia-Hao Cheng ,  Milind S. Bhagavat

IPC: H01L23/528 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065

Abstract: Various molded fan-out semiconductor chip devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a first molding layer that has internal conductor structures, a redistribution layer (RDL) structure positioned on the first molding layer and electrically connected to the internal conductor structures, a semiconductor chip positioned on and electrically connected to the RDL structure, and a second molding layer positioned on the RDL structure and at least partially encapsulating the semiconductor chip.

公开(公告)号：US20240063206A1

公开(公告)日：2024-02-22

申请号：US18497961

申请日：2023-10-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Milind Bhagavat ,  Brett Wilkerson ,  Rahul Agarwal

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0557 ,  H01L2224/08146

Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.