公开(公告)号：US12080632B2

公开(公告)日：2024-09-03

申请号：US17489182

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant Kulkarni ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Chintan Buch

IPC: H01L23/495 ,  H01L23/14 ,  H10B12/00

CPC classification number: H01L23/4951 ,  H01L23/145 ,  H10B12/50

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

公开(公告)号：US20230102183A1

公开(公告)日：2023-03-30

申请号：US17489182

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant Kulkarni ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Chintan Buch

IPC: H01L23/495 ,  H01L23/14

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

公开(公告)号：US20240006290A1

公开(公告)日：2024-01-04

申请号：US17854907

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriranga Sai Boyapati ,  Deepak Vasant Kulkarni ,  Rajasekaran Swaminathan

IPC: H01L23/498 ,  H01L23/64 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L23/642 ,  H01L23/645 ,  H01L21/4857 ,  H01L2224/73204 ,  H01L24/73

Abstract: An apparatus and method for efficiently transferring information as signals through a silicon package substrate. A semiconductor fabrication process (or process) begins with a relatively thin package substrate core layer and uses lasers to create openings in the package substrate at locations of the signal routes. The use of each of the relatively thin core layer and the lasers allows for reduction in the pitch of the signal routes. The process creates signal routes in the openings using stacked vias from one side of the package substrate to an opposite side of the package substrate. Additionally, the process forms the package substrate with multiple embedded passive components with different thicknesses in different layers of the package substrate. The embedded passive components are used to improve signal integrity of the signal routes.

公开(公告)号：US20250029900A1

公开(公告)日：2025-01-23

申请号：US18784143

申请日：2024-07-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant Kulkarni ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Chintan Buch

IPC: H01L23/495 ,  H01L23/14 ,  H10B12/00

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

公开(公告)号：US20240038596A1

公开(公告)日：2024-02-01

申请号：US17873591

申请日：2022-07-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Chandra Sekhar Mandalapu ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Richard T. Schultz

IPC: H01L21/84 ,  H01L21/02 ,  H01L23/14 ,  H01L23/498 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/02164 ,  H01L23/147 ,  H01L23/49827 ,  H01L27/1203

Abstract: An apparatus and method for efficiently increasing semiconductor chip functionality in a particular area. A semiconductor fabrication process (or process) grows a silicon substrate layer, and forms multiple p-type and n-type transistors along a front side surface of the silicon substrate layer. The process flips the silicon substrate layer and removes silicon substrate leaving a particular thickness of the silicon substrate layer. The process forms multiple p-type and n-type transistors along the back side surface of the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the back side surface to particular signals. The process forms through silicon vias (TSVs) that traverse through the silicon substrate layer. The process again flips the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the front side surface to particular signals.