公开(公告)号：US12174769B2

公开(公告)日：2024-12-24

申请号：US17705048

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Gurunath Dollin ,  Edoardo Prete ,  Milam Paraschou ,  Edward Wade Thoenes ,  Ryan J. Hensley ,  Gerald R. Talbot

IPC: G06F13/40 ,  G06F1/08 ,  G06F1/12 ,  G06F13/42 ,  H03K19/173

Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.

公开(公告)号：US20230305979A1

公开(公告)日：2023-09-28

申请号：US17705048

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Gurunath Dollin ,  Edoardo Prete ,  Milam Paraschou ,  Edward Wade Thoenes ,  Ryan J. Hensley ,  Gerald R. Talbot

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/12 ,  G06F1/08 ,  H03K19/173

CPC classification number: G06F13/4022 ,  G06F13/4282 ,  G06F13/4068 ,  G06F1/12 ,  G06F1/08 ,  H03K19/1737

Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.