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公开(公告)号：US20210111861A1
公开(公告)日：2021-04-15
申请号：US17128720
申请日：2020-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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Patent Agency Ranking
公开(公告)号：US10581587B1
公开(公告)日：2020-03-03
申请号：US16397848
申请日：2019-04-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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公开(公告)号：US12174769B2
公开(公告)日：2024-12-24
申请号：US17705048
申请日：2022-03-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Gurunath Dollin , Edoardo Prete , Milam Paraschou , Edward Wade Thoenes , Ryan J. Hensley , Gerald R. Talbot
IPC: G06F13/40 , G06F1/08 , G06F1/12 , G06F13/42 , H03K19/173
Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.
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公开(公告)号：US20200344039A1
公开(公告)日：2020-10-29
申请号：US16709472
申请日：2019-12-10
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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公开(公告)号：US20230305979A1
公开(公告)日：2023-09-28
申请号：US17705048
申请日：2022-03-25
Applicant: Advanced Micro Devices, Inc.
Inventor： Gurunath Dollin , Edoardo Prete , Milam Paraschou , Edward Wade Thoenes , Ryan J. Hensley , Gerald R. Talbot
IPC: G06F13/40 , G06F13/42 , G06F1/12 , G06F1/08 , H03K19/173
CPC classification number: G06F13/4022 , G06F13/4282 , G06F13/4068 , G06F1/12 , G06F1/08 , H03K19/1737
Abstract: Systems, apparatuses, and methods for implementing a periodic receiver clock data recovery scheme with dynamic data edge paths are disclosed. An IQ link calibration scheme performs a non-destructive data and edge path switch to determine an IQ offset without disturbing the data. A data path and an edge path pass through multiple stages of deserializers to widen the data path, with the deserializers clocked by clock divided versions of the original data and edge clocks. To initiate a calibration routine, the edge clock is aligned with the data clock, and then data and edge paths are swapped at a common point in a slower clock domain. The data path is then calibrated while the edge path carries the data signal. After the data path is calibrated, the edge and data paths are swapped back to the original configuration.
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公开(公告)号：US11283589B2
公开(公告)日：2022-03-22
申请号：US17128720
申请日：2020-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Varun Gupta , Milam Paraschou , Gerald R. Talbot , Gurunath Dollin , Damon Tohidi , Eric Ian Carpenter , Chad S. Gallun , Jeffrey Cooper , Hanwoo Cho , Thomas H. Likens, III , Scott F. Dow , Michael J. Tresidder
Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.
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