公开(公告)号：US20250118706A1

公开(公告)日：2025-04-10

申请号：US18377280

申请日：2023-10-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish DUBEY ,  Arsalan ALAM ,  Hemanth Kumar DHAVALESWARAPU ,  Chandra Sekhar MANDALAPU ,  Sriram CHANDRASEKARAN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/36 ,  H01L23/538 ,  H01L25/00

Abstract: A chip package and method for fabricating the same are provided that include a IC dies bonded to a thermal carrier having a plurality of metallic pillars. In one example, a chip package includes an interconnect routing structure and a first die disposed on a first surface of the interconnect routing structure. The first die has a circuitry connected to a circuitry of the interconnect routing structure. The chip package also includes a second die at least partially disposed over the first die. The second die has a circuitry connected to the circuitry of the first die. A thermal carrier is bonded on the second die. At least one of the thermal carrier, the first die, or the second die includes a plurality of metallic pillars configured to transfer heat, wherein the plurality of metallic pillars are electrically floating.

公开(公告)号：US20250079276A1

公开(公告)日：2025-03-06

申请号：US18241140

申请日：2023-08-31

Applicant: Advanced Micro Devices, Inc. ,  XILINX, INC.

Inventor： Manish DUBEY ,  Frank Peter LAMBRECHT ,  Brett P. WILKERSON ,  Deepak Vasant KULKARNI ,  Hemanth Kumar DHAVALESWARAPU ,  Priyal SHAH

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/043 ,  H01L25/065 ,  H05K1/14

Abstract: Disclosed herein is a chip package assembly that includes a package substrate coupled with an integrated circuit die, a stiffener attached to a top surface of the package substrate, and a connector assembly integrated with the stiffener. Both the connector assembly and the stiffener are disposed at a peripheral area of the top surface. The connector assembly includes a bracket and a connector. The connector is configured to connect with one or more optical cables or electrical connectors. The bracket may be formed by a cavity in the stiffener. The bracket may be attached to the top surface of the package substrate. The stiffener may be coupled with the bracket directly or via the connector. Additionally, a frame coupled to the stiffener or a PCB board may be used to secure the bracket in place.

公开(公告)号：US20240234304A1

公开(公告)日：2024-07-11

申请号：US18402688

申请日：2024-01-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Deepak Vasant KULKARNI ,  Samuel NAFFZIGER ,  Raja SWAMINATHAN ,  Matthew STRAAYER ,  Justin Michael BURKHART ,  Sri Ranga Sai BOYAPATI ,  Hemanth Kumar DHAVALESWARAPU ,  Alexander Helmut PFEIFFENBERGER ,  Manjunath D. HARITSA

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5227 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/29 ,  H01L25/0652 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/29009 ,  H01L2224/29025 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/15311

Abstract: Chip packages are described herein that includes chiplets embedded in a core of a substrate of the chip package, such as a package substrate or an interposer. In one example, the chiplet includes voltage regulation circuitry that is coupled through a substrate core embedded inductor to an integrated circuit (IC) die mounted to the substrate.