公开(公告)号：US20200133868A1

公开(公告)日：2020-04-30

申请号：US16176466

申请日：2018-10-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Maxim V. KAZAKOV

IPC: G06F12/0875 ,  G06F17/16 ,  G06F13/16

Abstract: A processor reduces bus bandwidth consumption by employing a shared load scheme, whereby each shared load retrieves data for multiple compute units (CUs) of a processor. Each CU in a specified group monitors a bus for load accesses directed to a cache shared by the multiple CUs. In response to identifying a load access on the bus, a CU determines if the load access is a shared load access for its share group. In response to identifying a shared load access for its share group, the CU allocates an entry of a private cache associated with the CU for data responsive to the shared load access. The CU then monitors the bus for the data targeted by the shared load. In response to identifying the targeted data on the bus, the CU stores the data at the allocated entry of the private cache.

公开(公告)号：US20190129756A1

公开(公告)日：2019-05-02

申请号：US15794593

申请日：2017-10-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Maxim V. KAZAKOV ,  Michael MANTOR

IPC: G06F9/50

Abstract: Footprints, or resource allocations, of waves within resources that are shared by processor cores in a multithreaded processor are measured concurrently with the waves executing on the processor cores. The footprints are averaged over a time interval. A number of waves are spawned and dispatched for execution in the multithreaded processor based on the average footprint. In some cases, the waves are spawned at a rate that is determined based on the average value of the footprints of waves within the resources. The rate of spawning waves is modified in response to a change in the average value of the footprints of the waves within the resources.

公开(公告)号：US20210343066A1

公开(公告)日：2021-11-04

申请号：US17230140

申请日：2021-04-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Maxim V. KAZAKOV ,  Mark FOWLER

IPC: G06T15/04 ,  G06T15/00

Abstract: A processor receives a request to access one or more levels of a partially resident texture (PRT) resource. The levels represent a texture at different levels of detail (LOD) and the request includes normalized coordinates indicating a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more residency maps that indicate texels that are resident in the PRT resource. The processor translates the normalized coordinates to texel coordinates in the one or more residency maps based on the offset and accesses, in response to the request, the one or more residency maps based on the texel coordinates to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource.

公开(公告)号：US20190066352A1

公开(公告)日：2019-02-28

申请号：US15687108

申请日：2017-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Maxim V. KAZAKOV ,  Skyler J. SALEH ,  Ruijin WU ,  Sagar Shankar BHANDARE

IPC: G06T15/00 ,  G06T15/04 ,  G06T15/80 ,  G06T9/00

Abstract: A pipeline is configured to access a memory that stores a texture block and metadata that encodes compression parameters of the texture block and a residency status of the texture block. A processor requests access to the metadata in conjunction with requesting data in the texture block to perform a shading operation. The pipeline selectively returns the data in the texture block to the processor depending on whether the metadata indicates that the texture block is resident in the memory. A cache can also be included to store a copy of the metadata that encodes the compression parameters of the texture block. The residency status and the metadata stored in the cache can be modified in response to requests to access the metadata stored in the cache.

公开(公告)号：US20220100528A1

公开(公告)日：2022-03-31

申请号：US17032307

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sateesh LAGUDU ,  Allen H. RUSH ,  Michael MANTOR ,  Arun Vaidyanathan ANANTHANARAYAN ,  Prasad NAGABHUSHANAMGARI ,  Maxim V. KAZAKOV

IPC: G06F9/38 ,  G06F13/40 ,  G06F13/28

Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that broadcast sets of the parameter values to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor includes single-instruction-multiple-data (SIMD) units including subsets of the processor element arrays in corresponding rows, workgroup processors (WGPs) including subsets of the SIMD units, and a memory fabric configured to interconnect with an external memory that stores the parameter values. The memory interfaces broadcast the parameter values to the SIMD units that include the processor element arrays in rows associated with the memory interfaces and columns of processor element arrays that are implemented across the SIMD units in the WGPs. The memory interfaces access the parameter values from the external memory via the memory fabric.

公开(公告)号：US20200250877A1

公开(公告)日：2020-08-06

申请号：US16723232

申请日：2019-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Maxim V. KAZAKOV ,  Mark FOWLER

IPC: G06T15/04 ,  G06T15/00

Abstract: A processor receives a request to access one or more levels of a partially resident texture (PRT) resource. The levels represent a texture at different levels of detail (LOD) and the request includes normalized coordinates indicating a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more residency maps that indicate texels that are resident in the PRT resource. The processor translates the normalized coordinates to texel coordinates in the one or more residency maps based on the offset and accesses, in response to the request, the one or more residency maps based on the texel coordinates to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource.