公开(公告)号：US09977609B2

公开(公告)日：2018-05-22

申请号：US15063186

申请日：2016-03-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Dong Ping Zhang ,  Paula Aguilera Diez

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F3/0613 ,  G06F3/0658 ,  G06F3/0673 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/10 ,  G06F2212/1024

Abstract: Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.

公开(公告)号：US10133672B2

公开(公告)日：2018-11-20

申请号：US15267097

申请日：2016-09-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Paula Aguilera Diez ,  Amin Farmahini-Farahani ,  Nuwan Jayasena

IPC: G06F12/00 ,  G06F12/0864 ,  G06F12/0804

Abstract: Described is a system and method for efficient pointer chasing in systems having a single memory node or a network of memory nodes. In particular, a pointer chasing command is sent along with a memory request by an issuing node to a memory node. The pointer chasing command indicates the number of interdependent memory accesses and information needed for the identified interdependent memory accesses. An address computing unit associated with the memory node determines the relevant memory address for an interdependent memory access absent further interaction with the issuing node or without having to return to the issuing node.

公开(公告)号：US20180074965A1

公开(公告)日：2018-03-15

申请号：US15267097

申请日：2016-09-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Paula Aguilera Diez ,  Amin Farmahini-Farahani ,  Nuwan Jayasena

IPC: G06F12/0864 ,  G06F12/0804

CPC classification number: G06F12/0864 ,  G06F12/0804 ,  G06F12/0815 ,  G06F12/0862 ,  G06F17/30 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/6028 ,  G06F2212/608

Abstract: Described is a system and method for efficient pointer chasing in systems having a single memory node or a network of memory nodes. In particular, a pointer chasing command is sent along with a memory request by an issuing node to a memory node. The pointer chasing command indicates the number of interdependent memory accesses and information needed for the identified interdependent memory accesses. An address computing unit associated with the memory node determines the relevant memory address for an interdependent memory access absent further interaction with the issuing node or without having to return to the issuing node.

公开(公告)号：US20170255397A1

公开(公告)日：2017-09-07

申请号：US15063186

申请日：2016-03-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Dong Ping Zhang ,  Paula Aguilera Diez

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F3/0613 ,  G06F3/0658 ,  G06F3/0673 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/10 ,  G06F2212/1024

Abstract: Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.