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公开(公告)号：US10037267B2
公开(公告)日：2018-07-31
申请号：US15299990
申请日：2016-10-21
CPC分类号： G06F11/3688 , G06F8/71 , G06F9/30101 , G06F9/448 , G06F9/4843 , G06F9/5088
摘要： Systems, apparatuses, and methods for migrating execution contexts are disclosed. A system includes a plurality of processing units and memory devices. The system is configured to execute any number of software applications. The system is configured to detect, within a first software application, a primitive for migrating at least a portion of the execution context of a source processing unit to a target processing unit, wherein the primitive includes one or more instructions. The execution context includes a plurality of registers. A first processing unit is configured to execute the one or more instructions of the primitive to cause a portion of an execution context of the first processing unit to be migrated to a second processing unit. In one embodiment, executing the primitive instruction(s) causes an instruction pointer value, with an optional offset value, to be sent to the second processing unit.
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公开(公告)号：US09977609B2
公开(公告)日：2018-05-22
申请号：US15063186
申请日：2016-03-07
CPC分类号： G06F3/0613 , G06F3/0658 , G06F3/0673 , G06F12/084 , G06F12/0888 , G06F12/10 , G06F2212/1024
摘要： Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.
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公开(公告)号：US10382410B2
公开(公告)日：2019-08-13
申请号：US14993455
申请日：2016-01-12
发明人： Nuwan Jayasena , Dong Ping Zhang
摘要： A processing system includes a processing module having a first interface coupleable to an interconnect. The first interface includes a first cryptologic engine to encrypt a representation of store data of a store operation and a memory address using a first key and a first feedback-based cryptologic process to generate first encrypted data and an encrypted memory address. A memory module includes a second interface coupled to the interconnect. The second interface includes a second cryptologic engine to decrypt the first encrypted data and the encrypted memory address using a second key and a second feedback-based cryptologic process to generate a copy of the representation of the store data and a copy of the memory address. The second interface further is to store the copy of the representation of the store data to a memory location of the memory core based on the copy of the memory address.
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公开(公告)号：US20170300592A1
公开(公告)日：2017-10-19
申请号：US15438401
申请日：2017-02-21
IPC分类号： G06F17/30
CPC分类号： G06F16/9014
摘要： Methods and mechanisms for managing data in a hash table are disclosed. A computing system includes a hash table configured to store data and hash management logic. In response to receiving a request to insert data into the hash table, the hash management logic is configured to generate a first hash value by applying a first hash function to the key of the key-value pair, and identify a first bucket within the hash table that corresponds to the first hash table. If the first bucket has a slot available, store the key-value pair in the slot. If the first bucket does not have a slot available, select a first slot of the first bucket for conversion to a remap entry, store the key-value pair in a second bucket, and store information associating the key-value pair with the second bucket in the remap entry.
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公开(公告)号：US20160086654A1
公开(公告)日：2016-03-24
申请号：US14492045
申请日：2014-09-21
发明人： Manish Arora , Indrani Paul , Yasuko Eckert , Nuwan Jayasena , Dong Ping Zhang
IPC分类号： G11C11/4096 , G11C5/02 , G11C11/4078
CPC分类号： G11C11/4096 , G11C5/025 , G11C7/04 , G11C8/12
摘要： A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.
摘要翻译： 管理存储器系统中的热水平的方法可以包括确定与存储器结构中的多个位置中的每一个相关联的预期热水平，以及针对存储器结构的多个操作的每个操作，将操作分配给 基于与操作相关联的热惩罚和与目标位置相关联的预期热水平，存储器结构中的多个物理位置的目标位置。
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公开(公告)号：US20180115496A1
公开(公告)日：2018-04-26
申请号：US15331002
申请日：2016-10-21
IPC分类号： H04L12/911 , H04L12/863
CPC分类号： H04L47/70 , G06F9/5066 , H04L47/50 , H04L67/10 , H04L67/2842 , Y02D10/22 , Y02D10/36
摘要： Systems, apparatuses, and methods for implementing mechanisms to improve data locality for distributed processing units are disclosed. A system includes a plurality of distributed processing units (e.g., GPUs) and memory devices. Each processing unit is coupled to one or more local memory devices. The system determines how to partition a workload into a plurality of workgroups based on maximizing data locality and data sharing. The system determines which subset of the plurality of workgroups to dispatch to each processing unit of the plurality of processing units based on maximizing local memory accesses and minimizing remote memory accesses. The system also determines how to partition data buffer(s) based on data sharing patterns of the workgroups. The system maps to each processing unit a separate portion of the data buffer(s) so as to maximize local memory accesses and minimize remote memory accesses.
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公开(公告)号：US20180113797A1
公开(公告)日：2018-04-26
申请号：US15299990
申请日：2016-10-21
CPC分类号： G06F11/3688 , G06F8/71 , G06F9/30101 , G06F9/448 , G06F9/4843 , G06F9/5088
摘要： Systems, apparatuses, and methods for migrating execution contexts are disclosed. A system includes a plurality of processing units and memory devices. The system is configured to execute any number of software applications. The system is configured to detect, within a first software application, a primitive for migrating at least a portion of the execution context of a source processing unit to a target processing unit, wherein the primitive includes one or more instructions. The execution context includes a plurality of registers. A first processing unit is configured to execute the one or more instructions of the primitive to cause a portion of an execution context of the first processing unit to be migrated to a second processing unit. In one embodiment, executing the primitive instruction(s) causes an instruction pointer value, with an optional offset value, to be sent to the second processing unit.
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公开(公告)号：US09947386B2
公开(公告)日：2018-04-17
申请号：US14492045
申请日：2014-09-21
发明人： Manish Arora , Indrani Paul , Yasuko Eckert , Nuwan Jayasena , Dong Ping Zhang
IPC分类号： G11C11/4078 , G11C11/4096 , G11C5/02 , G11C7/04 , G11C8/12
CPC分类号： G11C11/4096 , G11C5/025 , G11C7/04 , G11C8/12
摘要： A method of managing thermal levels in a memory system may include determining an expected thermal level associated with each of a plurality of locations in a memory structure, and for each operation of a plurality of operations addressed to the memory structure, assigning the operation to a target location of the plurality of physical locations in the memory structure based on a thermal penalty associated with the operation and the expected thermal level associated with the target location.
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公开(公告)号：US10528613B2
公开(公告)日：2020-01-07
申请号：US14948892
申请日：2015-11-23
发明人： Dong Ping Zhang
IPC分类号： G06F16/50 , G06F16/2458 , G06F16/2457 , G06F16/53 , G06F16/583
摘要： A method and apparatus for performing a search in a processor-in-memory (PIM) system having a first processor and at least one memory module includes receiving one or more images by the first processor. The first processor sends a query for a search of memory for a matching image to the one or more images to at least one memory module, which searches memory in the memory module, in response to the received query. The at least one memory module sends the results of the search to the first processor, and the first processor performs a comparison of the received results from the at least one memory module to the received one or more images.
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10.发明申请公开(公告)号：US20170255397A1
公开(公告)日：2017-09-07
申请号：US15063186
申请日：2016-03-07
CPC分类号： G06F3/0613 , G06F3/0658 , G06F3/0673 , G06F12/084 , G06F12/0888 , G06F12/10 , G06F2212/1024
摘要： Systems, apparatuses, and methods for implementing efficient queues and other data structures. A queue may be shared among multiple processors and/or threads without using explicit software atomic instructions to coordinate access to the queue. System software may allocate an atomic queue and corresponding queue metadata in system memory and return, to the requesting thread, a handle referencing the queue metadata. Any number of threads may utilize the handle for accessing the atomic queue. The logic for ensuring the atomicity of accesses to the atomic queue may reside in a management unit in the memory controller coupled to the memory where the atomic queue is allocated.
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