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公开(公告)号:US11969600B2
公开(公告)日:2024-04-30
申请号:US17355677
申请日:2021-06-23
Applicant: ADVANCED NEUROMODULATION SYSTEMS, INC.
Inventor: Daran DeShazo , Gavin Rade
CPC classification number: A61N1/37235 , A61N1/37223 , A61N1/378 , A61B5/367 , A61N1/36038 , A61N1/36053 , A61N1/36062 , A61N1/36082 , A61N1/362 , A61N1/38 , A61N1/39622 , A61N2/006
Abstract: An implantable medical device (IMD) includes one or more stimulation engines (SEs) and selectively connectable output switching circuitry for driving a plurality of output nodes associated with a respective plurality of electrodes of the IMD's lead system when implanted in a patient. The output switching circuitry may be configured to facilitate self-test mode (STM) functionality in the IMD (e.g., when it is in a hermetically sealed package) by using a dual mode switch in series with a stimulation engine selection switch with respect to each output node in the output switching circuitry under mode selection control.
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公开(公告)号:US11426588B2
公开(公告)日:2022-08-30
申请号:US16855211
申请日:2020-04-22
Applicant: Advanced Neuromodulation Systems, Inc.
Inventor: Gavin Rade , Daran DeShazo
Abstract: The present disclosure provides systems and methods for generating waveforms for an implantable pulse generator of a neurostimulation system. A waveform generation system includes a computing device, at least one buffer memory, and at least one programmable current regulator. The at least one buffer memory is coupled between the computing device and the at least one programmable current regulator. The computing device is configured to load a string of output current values into the at least one buffer memory, and the at least one buffer memory is configured to sequentially feed each output current value to the at least one programmable current regulator. Further, the at least one programmable current regulator is configured to control current supplied to a plurality of electrodes based on the received output current values.
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3.
公开(公告)号:US20230066914A1
公开(公告)日:2023-03-02
申请号:US17405804
申请日:2021-08-18
Applicant: ADVANCED NEUROMODULATION SYSTEMS, INC.
Inventor: Gavin Rade , Daran DeShazo
Abstract: An implantable medical device (IMD) configured to provide stimulation therapy using an instruction set architecture (ISA) includes a main processor operating at a first frequency and a secondary processor operating at a second frequency lower than the first frequency. Example ISA may comprise assembly-language-like instructions that may be executed by the secondary processor for configuring one or more stimulation engines (SEs) to cause stimulation of select electrode sets of a lead system based on one or more pulse definitions and one or more timing definitions corresponding to a therapy program selection effectuated by a user at an external device.
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公开(公告)号:US20220409911A1
公开(公告)日:2022-12-29
申请号:US17355677
申请日:2021-06-23
Applicant: ADVANCED NEUROMODULATION SYSTEMS, INC.
Inventor: Daran DeShazo , Gavin Rade
Abstract: An implantable medical device (IMD) includes one or more stimulation engines (SEs) and selectively connectable output switching circuitry for driving a plurality of output nodes associated with a respective plurality of electrodes of the IMD's lead system when implanted in a patient. The output switching circuitry may be configured to facilitate self-test mode (STM) functionality in the IMD (e.g., when it is in a hermetically sealed package) by using a dual mode switch in series with a stimulation engine selection switch with respect to each output node in the output switching circuitry under mode selection control.
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5.
公开(公告)号:US12005257B2
公开(公告)日:2024-06-11
申请号:US17405804
申请日:2021-08-18
Applicant: ADVANCED NEUROMODULATION SYSTEMS, INC.
Inventor: Gavin Rade , Daran DeShazo
CPC classification number: A61N1/36167 , A61N1/025 , A61N1/36132 , A61N1/37223 , A61N1/37247
Abstract: An implantable medical device (IMD) configured to provide stimulation therapy using an instruction set architecture (ISA) includes a main processor operating at a first frequency and a secondary processor operating at a second frequency lower than the first frequency. Example ISA may comprise assembly-language-like instructions that may be executed by the secondary processor for configuring one or more stimulation engines (SEs) to cause stimulation of select electrode sets of a lead system based on one or more pulse definitions and one or more timing definitions corresponding to a therapy program selection effectuated by a user at an external device.
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公开(公告)号:US20230256234A1
公开(公告)日:2023-08-17
申请号:US17673091
申请日:2022-02-16
Applicant: Advanced Neuromodulation Systems, Inc.
Inventor: Daran DeShazo , Gavin Rade
CPC classification number: A61N1/025 , A61N1/36171 , A61N1/36153 , A61N1/36125 , A61N1/36175 , A61N1/36178 , A61N1/36067 , A61N1/36071
Abstract: Pulse pattern detecting circuitry for use with a fractional voltage multiplier of a neurostimulation system is provided. The pulse pattern detecting circuitry is configured to detect an initial overlap of a repeating pulse pattern, wherein the repeating pulse pattern is generated by a plurality of pulse engines that generate pulses at different frequencies, the initial overlap occurring when pulses generated by each of the plurality of pulse engines occur simultaneously, detect a subsequent overlap of the repeating pulse pattern, the subsequent overlap of the pulse pattern occurring when pulses generated by each of the plurality of pulse engines again occur simultaneously, detect a plurality of events between the initial overlap and the subsequent overlap, each event corresponding to at least one of the plurality of pulse engines generating a pulse, and record a voltage multiplier setting for each of the plurality of detected events.
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公开(公告)号:US20210330982A1
公开(公告)日:2021-10-28
申请号:US16855211
申请日:2020-04-22
Applicant: Advanced Neuromodulation Systems, Inc
Inventor: Gavin Rade , Daran DeShazo
Abstract: The present disclosure provides systems and methods for generating waveforms for an implantable pulse generator of a neurostimulation system. A waveform generation system includes a computing device, at least one buffer memory, and at least one programmable current regulator. The at least one buffer memory is coupled between the computing device and the at least one programmable current regulator. The computing device is configured to load a string of output current values into the at least one buffer memory, and the at least one buffer memory is configured to sequentially feed each output current value to the at least one programmable current regulator. Further, the at least one programmable current regulator is configured to control current supplied to a plurality of electrodes based on the received output current values.
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