公开(公告)号：US11817397B2

公开(公告)日：2023-11-14

申请号：US17129641

申请日：2020-12-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chi Sheng Tseng ,  Lu-Ming Lai ,  Hui-Chung Liu ,  Yu-Che Huang

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/50 ,  G01L1/26 ,  H01R12/61 ,  H01L21/60

CPC classification number: H01L23/562 ,  G01L1/26 ,  H01L21/50 ,  H01L23/5387 ,  H01L24/80 ,  H01R12/61 ,  H01L2021/60135

Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a sensor module, a connector, and a stress buffer structure. The sensor module is disposed on the carrier. The connector is connected to the carrier. The stress buffer structure connects the connector to the sensor module.

公开(公告)号：US11410915B2

公开(公告)日：2022-08-09

申请号：US17088449

申请日：2020-11-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Che Huang ,  Chang Chin Tsai

IPC: H01L23/495 ,  H01L23/48 ,  H01L23/28 ,  H01L21/00 ,  H05K7/00 ,  H05K7/18 ,  H01R9/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a carrier, a first encapsulant, and an interposer. The first encapsulant is on the carrier and defines a cavity. The interposer is disposed between the first encapsulant and the cavity. The first encapsulant covers a portion of the interposer.

公开(公告)号：US11495511B2

公开(公告)日：2022-11-08

申请号：US17006664

申请日：2020-08-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Che Huang ,  Lu-Ming Lai ,  Ying-Chung Chen

IPC: H01L23/32 ,  H01L23/498 ,  H01L21/48

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a semiconductor package device, a first constraint structure and a second constraint structure. The first constraint structure is connected to the semiconductor package device. The second constraint structure is connected to the semiconductor package device and under a projection of the semiconductor package device.

公开(公告)号：US11430906B2

公开(公告)日：2022-08-30

申请号：US16518792

申请日：2019-07-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chin Tsai ,  Yu-Che Huang ,  Hsun-Wei Chan

IPC: H01L31/12

Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.

公开(公告)号：US12085768B2

公开(公告)日：2024-09-10

申请号：US17465713

申请日：2021-09-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shih-Chieh Tang ,  Lu-Ming Lai ,  Yu-Che Huang ,  Ying-Chung Chen

IPC: G02B6/42

CPC classification number: G02B6/4215 ,  G02B6/4214

Abstract: The present disclosure provides an optical module. The optical module includes an optical component disposed in or on a carrier and configured to receive a first light. The optical component is further configured to transmit a second light to a first portion of the carrier and transmit a third light to a second portion of the carrier.

公开(公告)号：US12094995B2

公开(公告)日：2024-09-17

申请号：US17899552

申请日：2022-08-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chin Tsai ,  Yu-Che Huang ,  Hsun-Wei Chan

IPC: H01L31/12

CPC classification number: H01L31/125

Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.

公开(公告)号：US12040422B2

公开(公告)日：2024-07-16

申请号：US17899552

申请日：2022-08-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chang Chin Tsai ,  Yu-Che Huang ,  Hsun-Wei Chan

IPC: H01L31/12

CPC classification number: H01L31/125

Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.

公开(公告)号：US11562969B2

公开(公告)日：2023-01-24

申请号：US16569228

申请日：2019-09-12

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Che Huang ,  Lu-Ming Lai

IPC: H01L23/49 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor device package and a method for packaging the same are provided. A semiconductor device package includes a carrier, an electronic component, a buffer layer, a reinforced structure, and an encapsulant. The electronic component is disposed over the carrier and has an active area. The buffer layer is disposed on the active area of the electronic component. The reinforced structure is disposed on the buffer layer. The encapsulant encapsulates the carrier, the electronic component and the reinforced structure.

公开(公告)号：US11133278B2

公开(公告)日：2021-09-28

申请号：US16583006

申请日：2019-09-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Che Huang ,  Ching-Han Huang ,  An-Nong Wen ,  Po-Ming Huang

IPC: H01L23/00 ,  H01L21/768

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, a cap layer, a conductive terminal, and a dam structure. The semiconductor die has a first surface. The cap layer is over the semiconductor die and has a second surface facing the first surface of the semiconductor die. The conductive terminal penetrates the cap layer and electrically connects to the semiconductor die. The dam structure is between the semiconductor die and the cap layer and surrounds a portion of the conductive terminal between the first surface and the second surface, thereby forming a gap between the cap layer and the semiconductor die.