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公开(公告)号：US20070139088A1
公开(公告)日：2007-06-21
申请号：US11680026
申请日：2007-02-28
申请人： Akhil Garlapati , Lizhong Sun , Douglas Pastorello , Richard Juhn , Axel Thomsen
发明人： Akhil Garlapati , Lizhong Sun , Douglas Pastorello , Richard Juhn , Axel Thomsen
IPC分类号： H03K23/00
CPC分类号： H03K23/66 , H03K21/10 , H03L7/0805 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/193 , H03L7/1974 , H03L7/1976
摘要： In at least one embodiment of the invention, a method for dividing a first signal having a first frequency by a divide ratio to generate a lower frequency signal includes generating a first plurality of signals having a common frequency, a first pulse width, and different phases. The first plurality of signals is based, at least in part, on at least one signal having a second pulse width. The first pulse width is selected from a plurality of pulse widths based, at least in part, on the divide ratio. The method includes sequentially selecting individual pulses of the first plurality of signals as an output signal of a select circuit to generate an output signal having a frequency lower than the first frequency.
摘要翻译： 在本发明的至少一个实施例中，一种用于将具有第一频率的第一信号除以分频比以产生较低频率信号的方法包括产生具有共同频率，第一脉冲宽度和不同相位的第一多个信号 。 第一组多个信号至少部分地基于具有第二脉冲宽度的至少一个信号。 至少部分地基于分频比，从多个脉冲宽度中选择第一脉冲宽度。 该方法包括顺序选择第一多个信号中的各个脉冲作为选择电路的输出信号，以产生具有低于第一频率的频率的输出信号。
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公开(公告)号：US20050242848A1
公开(公告)日：2005-11-03
申请号：US10878198
申请日：2004-06-28
申请人： Lizhong Sun , Douglas Pastorello , Richard Juhn , Axel Thomsen
发明人： Lizhong Sun , Douglas Pastorello , Richard Juhn , Axel Thomsen
CPC分类号： H03K23/66 , H03L7/193 , H03L7/1976
摘要： A phase selectable divider circuit includes a select circuit receiving a plurality of signals having a common frequency and a different phase. One of the plurality of signals, having a first phase, is selected as a selector circuit output signal. A first value corresponding to the first phase is summed with a second value corresponding to a phase offset from the first phase to generate a sum indicative thereof. That sum is used to select a second one of the signals having a second phase as the next selector circuit output signal. As successive sums are generated, a pulse train is supplied by selector circuit having a desired frequency.
摘要翻译： 相位选择分频电路包括接收具有共同频率和不同相位的多个信号的选择电路。 选择具有第一相位的多个信号中的一个作为选择器电路输出信号。 对应于第一相位的第一值与对应于从第一相位的相位偏移的第二值相加，以产生指示其的和。 该和用于选择具有第二相位的第二信号作为下一个选择器电路输出信号。 当产生连续的和时，由选择器电路提供具有期望频率的脉冲串。
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公开(公告)号：US07562275B2
公开(公告)日：2009-07-14
申请号：US11531832
申请日：2006-09-14
CPC分类号： G01R31/31713 , G01R1/0408 , G01R31/31701 , G01R31/318544
摘要： A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input level. The technique substantially reduces or eliminates false detections of the test mode and substantially reduces or eliminates falsely enabling other (e.g., functional) mode(s) of the integrated circuit.
摘要翻译： 用于增加集成电路的终端的功能而不增加集成电路的终端数量的技术利用至少一个三电平终端和转换器电路，其提供指示集成电路的测试模式的逻辑电平，以响应于 相应的输入电平。 该技术基本上减少或消除了测试模式的错误检测，并且基本上减少或消除了错误地启用集成电路的其他（例如，功能）模式。
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公开(公告)号：US20080091992A1
公开(公告)日：2008-04-17
申请号：US11531832
申请日：2006-09-14
IPC分类号： G01R31/28
CPC分类号： G01R31/31713 , G01R1/0408 , G01R31/31701 , G01R31/318544
摘要： A technique for increasing functionality of terminals of an integrated circuit without increasing the number of terminals of the integrated circuit utilizes at least one tri-level terminal and converter circuit that provides a logic level indicative of a test mode of the integrated circuit in response to a corresponding input level. The technique substantially reduces or eliminates false detections of the test mode and substantially reduces or eliminates falsely enabling other (e.g., functional) mode(s) of the integrated circuit.
摘要翻译： 用于增加集成电路的终端的功能而不增加集成电路的终端数量的技术利用至少一个三电平终端和转换器电路，其提供指示集成电路的测试模式的逻辑电平，以响应于 相应的输入电平。 该技术基本上减少或消除了测试模式的错误检测，并且基本上减少或消除了错误地启用集成电路的其他（例如，功能）模式。
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