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    Page table search engine
    1.
    发明授权
    Page table search engine 有权

    公开(公告)号：US10762137B1

    公开(公告)日：2020-09-01

    申请号：US15814306

    申请日：2017-11-15

    Applicant: Amazon Technologies, Inc.

    Inventor： Thomas A. Volpe ,  Steven Scott Larson

    IPC: G06F17/30 ,  G06F16/903 ,  G06F12/02 ,  G06F16/901

    Abstract: Provided are systems and methods for an integrated circuit comprising a search engine, which a memory controller can use to manage a page table. In various implementations, the search engine can generate a series of read transactions to read the page table, which is stored in a memory. Each page table entry includes an address translation for processor memory. The memory controller may periodically change the address translations. The search engine can further determine whether data read from an entry in the page table corresponds to a search parameter. The search engine can further output a response, where the response is affirmative when the data read from the entry corresponds to the search parameters, and where the response is negative when no data read from any entry corresponds to the search parameter.

    Address translation for storage class memory in a system that includes virtual machines
    2.
    发明授权
    Address translation for storage class memory in a system that includes virtual machines 有权

    公开(公告)号：US10754789B1

    公开(公告)日：2020-08-25

    申请号：US15814300

    申请日：2017-11-15

    Applicant: Amazon Technologies, Inc.

    Inventor： Thomas A. Volpe ,  Steven Scott Larson

    IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/14 ,  G06F12/123 ,  G06F13/16 ,  G06F12/1018 ,  G06F9/455 ,  G06F12/1009

    Abstract: Provided are systems and methods for an address translation circuit for a memory controller. The address translation circuit can include an address translation table. A first set of rows in the address translation table can be associated with all virtual machine identifiers supported by the memory controller. A second set of rows can be associated with only a particular virtual machine identifier. The address translation circuit can receive an input address for a transaction to processor memory. The address translation circuit can determine an index by inputting the input address into a hash function. The address translation circuit can read a row from the address translation table using the index. The address translation circuit can determine whether an entry in the row includes the address translation for the input address. The address translation circuit can generate and output a translated address using the address translation.

    Tracking persistent memory usage
    5.
    发明授权
    Tracking persistent memory usage 有权

    公开(公告)号：US11314635B1

    公开(公告)日：2022-04-26

    申请号：US15838934

    申请日：2017-12-12

    Applicant: Amazon Technologies, Inc.

    Inventor： Thomas A. Volpe ,  Mark Anthony Banse ,  Steven Scott Larson

    IPC: G06F3/06 ,  G06F12/02 ,  G06F11/34 ,  G06F12/1027 ,  G06F11/10 ,  G06F13/16

    Abstract: Disclosed herein are techniques for tracking usage of a storage-class memory. In one embodiment, a method includes receiving a first statistics update entry and a second statistics update entry by a memory controller for a memory, and assembling the statistics update entries into a statistics log entry. The first statistics update entry indicates a number of operations performed on a first memory block in the memory, and the second statistics update entry indicates a number of operations performed on a second memory block in the memory. The method also includes determining a persistent memory region in a persistent memory for storing the statistics log entry, and writing the statistics log entry into the persistent memory region, where the statistics log entry persists in the persistent memory region until the statistics log entry is read back through the memory controller.

    Address translation and address translation memory for storage class memory
    7.
    发明授权
    Address translation and address translation memory for storage class memory 有权

    公开(公告)号：US10810133B1

    公开(公告)日：2020-10-20

    申请号：US15814303

    申请日：2017-11-15

    Applicant: Amazon Technologies, Inc.

    Inventor： Thomas A. Volpe ,  Steven Scott Larson

    IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/123 ,  G06F12/128

    Abstract: Provided are systems and methods for an address translation circuit for a memory controller. In various implementations, the address translation circuit includes an address translation table operable to include a subset of address translations for a processor memory. An address translation memory can include all address translations for the processor memory. The address translation circuit can be operable to receive an input address for a transaction to processor memory. The address translation circuit can determine an index for the address translation table by inputting the input address into a hash function. The address translation circuit can read a row from the address translation table using the index. The address translation circuit can determine whether an entry in the row includes an address translation for the input address. The address translation can generate and output a translated address using the address translation.

    Write failure handling for a memory controller to non-volatile memory
    8.
    发明授权
    Write failure handling for a memory controller to non-volatile memory 有权

    公开(公告)号：US10459662B1

    公开(公告)日：2019-10-29

    申请号：US15717759

    申请日：2017-09-27

    Applicant: Amazon Technologies, Inc.

    Inventor： Thomas A. Volpe ,  Mark Anthony Banse ,  Steven Scott Larson

    IPC: G06F3/06 ,  G06F12/1009

    Abstract: Failed write handling can be implemented at a memory controller for non-volatile memory. Failure of a write to a storage location in the non-volatile memory may be detected. An indication of the failure may be sent to a microcontroller for the non-volatile memory which may return an instruction to write to a different location in the non-volatile memory. Reads and writes to the storage location of the failed write may still be allowed, in some embodiments, by redirecting the reads and writes to a copy of data of the failed write stored in a copy buffer in the memory controller.

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