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    PHOTOSENSITISING COMPOSITION AND ITS USES
    2.
    发明申请
    PHOTOSENSITISING COMPOSITION AND ITS USES 审中-公开
    光敏组合物及其用途

    公开(公告)号：US20110027384A1

    公开(公告)日：2011-02-03

    申请号：US12936126

    申请日：2009-04-06

    申请人： Anil Kishen ,  Saji George

    发明人： Anil Kishen ,  Saji George

    IPC分类号： A61K33/40 ,  A61K31/025 ,  A61K31/03 ,  A61K31/02 ,  A61K31/662 ,  A61K33/20 ,  A61K31/10 ,  A61P31/00

    摘要： The present invention provides a photosensitising composition comprising a mixture of at least one oxygen carrier, at least one oxidising agent and at least one surfactant, and its uses. The ratio of the at least one oxygen carrier to the at least one oxidising agent to the at least one surfactant may be in the range of 50:40:10 to 80:19.8:0.2. The photosensitising composition may be used for treating and/or preventing conditions caused by microorganisms.

    摘要翻译： 本发明提供了包含至少一种氧载体，至少一种氧化剂和至少一种表面活性剂的混合物的光敏组合物及其用途。 至少一种氧载体与至少一种氧化剂与至少一种表面活性剂的比例可以在50:40:10至80:19.8:0.2的范围内。 光敏组合物可用于治疗和/或预防微生物引起的病症。

    Photosensitising composition and its uses
    3.
    发明授权
    Photosensitising composition and its uses 有权

    公开(公告)号：US10568961B2

    公开(公告)日：2020-02-25

    申请号：US12936126

    申请日：2009-04-06

    申请人： Anil Kishen ,  Saji George

    发明人： Anil Kishen ,  Saji George

    IPC分类号： A61K41/00 ,  A61K6/00 ,  A61K9/00

    摘要： The present invention provides a photosensitising composition comprising a mixture of at least one oxygen carrier, at least one oxidising agent and at least one surfactant, and its uses. The ratio of the at least one oxygen carrier to the at least one oxidising agent to the at least one surfactant may be in the range of 50:40:10 to 80:19.8:0.2. The photosensitising composition may be used for treating and/or preventing conditions caused by microorganisms.

    MULTI-BIT FLIP-FLOP WITH ENHANCED FAULT DETECTION
    4.
    发明申请
    MULTI-BIT FLIP-FLOP WITH ENHANCED FAULT DETECTION 有权
    具有增强故障检测功能的多位片浮标

    公开(公告)号：US20160065185A1

    公开(公告)日：2016-03-03

    申请号：US14472809

    申请日：2014-08-29

    申请人： Anis M. Jarrar ,  John M. Boyer ,  Saji George ,  David R. Tipple

    发明人： Anis M. Jarrar ,  John M. Boyer ,  Saji George ,  David R. Tipple

    IPC分类号： H03K3/037 ,  H03K19/20 ,  G06F11/07 ,  H03K19/0175

    CPC分类号： H03K3/0375 ,  G06F11/0721 ,  G06F11/0772 ,  H03K3/0372 ,  H03K19/0175 ,  H03K19/20

    摘要： A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.

    摘要翻译： 处理系统包括在处理器核心和外围部件中的至少一个中的处理器核心，外围部件和触发器单元。 触发器单元可以包括主锁存器和耦合到主锁存器的输出的两个从锁存器。 第一从锁存器形成在半导体衬底的第一掺杂阱区上。 第二从锁存器形成在半导体衬底的第二掺杂阱区上。 比较器耦合到第一从锁存器的输出端和第二从锁存器的输出端。 比较器的输出指示存储在第一从锁存器中的状态是否与存储在第二从锁存器中的状态相同。

    Multi-bit flip-flop with enhanced fault detection
    7.
    发明授权
    Multi-bit flip-flop with enhanced fault detection 有权
    具有增强故障检测功能的多位触发器

    公开(公告)号：US09264021B1

    公开(公告)日：2016-02-16

    申请号：US14472809

    申请日：2014-08-29

    申请人： Anis M. Jarrar ,  John M. Boyer ,  Saji George ,  David R. Tipple

    发明人： Anis M. Jarrar ,  John M. Boyer ,  Saji George ,  David R. Tipple

    IPC分类号： H03K19/003 ,  H03K3/037 ,  H03K19/0175 ,  H03K19/20 ,  G06F11/07

    CPC分类号： H03K3/0375 ,  G06F11/0721 ,  G06F11/0772 ,  H03K3/0372 ,  H03K19/0175 ,  H03K19/20

    摘要： A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.

    摘要翻译： 处理系统包括在处理器核心和外围部件中的至少一个中的处理器核心，外围部件和触发器单元。 触发器单元可以包括主锁存器和耦合到主锁存器的输出的两个从锁存器。 第一从锁存器形成在半导体衬底的第一掺杂阱区上。 第二从锁存器形成在半导体衬底的第二掺杂阱区上。 比较器耦合到第一从锁存器的输出端和第二从锁存器的输出端。 比较器的输出指示存储在第一从锁存器中的状态是否与存储在第二从锁存器中的状态相同。