公开(公告)号：US20240103557A1

公开(公告)日：2024-03-28

申请号：US17947465

申请日：2022-09-19

Applicant: Apple Inc.

Inventor： Giulio Maria Iadicicco ,  Angelo Bassi

IPC: G05F3/26

CPC classification number: G05F3/265

Abstract: A bandgap circuit that is area efficient and has a low power consumption. The bandgap circuit includes a voltage generator circuit, and a sample and hold circuit coupled to the voltage generator circuit. The voltage generator circuit includes a pair of transistors each connected in a diode configuration and biased with a respective current source of a plurality of current sources of the voltage generator circuit. During a sample phase, the sample and hold circuit samples a first voltage between a first base and a first emitter of a first transistor of the pair of transistors and a second voltage between a second base and a second emitter of a second transistor of the pair of transistors. During a hold phase subsequent to the sample phase, the sample and hold circuit generates an output voltage as a combination of the sampled first and second voltages.

公开(公告)号：US12111676B2

公开(公告)日：2024-10-08

申请号：US17947465

申请日：2022-09-19

Applicant: Apple Inc.

Inventor： Giulio Maria Iadicicco ,  Angelo Bassi

IPC: G05F3/26

CPC classification number: G05F3/265

Abstract: A bandgap circuit that is area efficient and has a low power consumption. The bandgap circuit includes a voltage generator circuit, and a sample and hold circuit coupled to the voltage generator circuit. The voltage generator circuit includes a pair of transistors each connected in a diode configuration and biased with a respective current source of a plurality of current sources of the voltage generator circuit. During a sample phase, the sample and hold circuit samples a first voltage between a first base and a first emitter of a first transistor of the pair of transistors and a second voltage between a second base and a second emitter of a second transistor of the pair of transistors. During a hold phase subsequent to the sample phase, the sample and hold circuit generates an output voltage as a combination of the sampled first and second voltages.

公开(公告)号：US20240283450A1

公开(公告)日：2024-08-22

申请号：US18172871

申请日：2023-02-22

Applicant: Apple Inc.

Inventor： Gary Seigneuret ,  Giulio Maria Iadicicco ,  Maria Khukhryanskaya ,  Emmanuela M. Campolo

IPC: H03K17/693 ,  G06F1/26

CPC classification number: H03K17/693 ,  G06F1/26 ,  H03K19/018521

Abstract: A multiplex circuit for computer systems includes multiple bootstrap switches that share a common capacitor for generating a boost voltage. When one of the bootstrap switches is activated, it is coupled to the common capacitor which is used to generate the boost voltage to control a switch transistor in the activated bootstrap circuit. Upon deactivating an active bootstrap switch, the common capacitor is pre-charged prior to the activation of another bootstrap switch.

公开(公告)号：US11777398B2

公开(公告)日：2023-10-03

申请号：US17144902

申请日：2021-01-08

Applicant: Apple Inc.

Inventor： Giulio Maria Iadicicco ,  Michael Couleur ,  Siarhei Meliukh

IPC: H02M1/08 ,  H03K17/687 ,  H02M3/158 ,  H03K17/06 ,  H02M1/00

CPC classification number: H02M1/08 ,  H02M3/158 ,  H03K17/6872 ,  H02M1/0006 ,  H03K17/063

Abstract: Circuitry for bootstrapping and precharging a gate of a field-effect transistor (FET) is disclosed. In one embodiment, an apparatus includes a first transistor coupled to a switching node and further coupled to receive a supply voltage from a supply voltage node, and a second transistor coupled between the switching node and a ground node, wherein the first and second transistors are of a same type. A precharge circuit is configured to precharge a gate terminal of the first transistor to a voltage that is less than a supply voltage on the voltage supply node. The apparatus also includes a bootstrap circuit. Subsequent to precharging the gate terminal of the first transistor, the bootstrap circuit is configured to cause activation of the first transistor by charging the gate terminal to a voltage greater than the supply voltage.

公开(公告)号：US20220224216A1

公开(公告)日：2022-07-14

申请号：US17144902

申请日：2021-01-08

Applicant: Apple Inc.

Inventor： Giulio Maria Iadicicco ,  Michael Couleur ,  Siarhei Meliukh

IPC: H02M1/08 ,  H02M3/158 ,  H03K17/687

Abstract: Circuitry for bootstrapping and precharging a gate of a field-effect transistor (FET) is disclosed. In one embodiment, an apparatus includes a first transistor coupled to a switching node and further coupled to receive a supply voltage from a supply voltage node, and a second transistor coupled between the switching node and a ground node, wherein the first and second transistors are of a same type. A precharge circuit is configured to precharge a gate terminal of the first transistor to a voltage that is less than a supply voltage on the voltage supply node. The apparatus also includes a bootstrap circuit. Subsequent to precharging the gate terminal of the first transistor, the bootstrap circuit is configured to cause activation of the first transistor by charging the gate terminal to a voltage greater than the supply voltage.