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公开(公告)号:US10346328B2
公开(公告)日:2019-07-09
申请号:US15700838
申请日:2017-09-11
Applicant: Apple Inc.
Inventor: James D. Ramsay , Inder Sodhi
Abstract: An interrupt mechanism is disclosed. In one embodiment an integrated circuit (IC) is coupled to a number of peripheral devices, via a bus, and includes an interface controller. The interface controller includes a bus engine circuit coupled to receive data from the various ones of the peripheral devices, wherein the data may include various requests. The bus engine circuit also includes decoding circuitry configured to decode the data to determine the nature of the requests. Responsive to determining that interrupt information is stored in one or more of the requests, the interrupt information may be written to one of a number of interrupt registers. An interrupt controller may read the interrupt registers to determine the presence of interrupts, and thus initiate the process to see that they are serviced.
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公开(公告)号:US20190079884A1
公开(公告)日:2019-03-14
申请号:US15700838
申请日:2017-09-11
Applicant: Apple Inc.
Inventor: James D. Ramsay , Inder Sodhi
CPC classification number: G06F13/24 , G06F13/1642 , G06F13/22 , G06F13/4282
Abstract: An interrupt mechanism is disclosed. In one embodiment an integrated circuit (IC) is coupled to a number of peripheral devices, via a bus, and includes an interface controller. The interface controller includes a bus engine circuit coupled to receive data from the various ones of the peripheral devices, wherein the data may include various requests. The bus engine circuit also includes decoding circuitry configured to decode the data to determine the nature of the requests. Responsive to determining that interrupt information is stored in one or more of the requests, the interrupt information may be written to one of a number of interrupt registers. An interrupt controller may read the interrupt registers to determine the presence of interrupts, and thus initiate the process to see that they are serviced.
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