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公开(公告)号：US20240313716A1
公开(公告)日：2024-09-19
申请号：US18121426
申请日：2023-03-14
Applicant: Apple Inc.
Inventor： Milad Darvishi , Seyed Milad Moosavifar , Morteza Nick , Yi Zhao
CPC classification number: H03F3/245 , H03F1/565 , H03F3/45475 , H03F2200/294 , H03F2200/451
Abstract: This disclosure is directed to amplifiers including amplification circuitry, phase-shifting circuitry, and impedance matching circuitry. An amplifier may include multiple amplifier stages each amplifying an input signal by a portion of a total amplification factor of the amplifier. The amplifier may include multiple phase shifters each including a matching circuit embedded thereon. Each phase shifter may shift a phase of the input signal by a portion of a total phase shift value of the amplifier. Moreover, at least some phase shifters may provide an output signal at an output port having an output impedance matching (e.g., nearly matching) an input impedance of a subsequent circuit coupled thereto. The amplifier may include cascaded amplifier stages and phase shifters coupled to the subsequent circuit such as an antenna, a processor, and/or a memory device.
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公开(公告)号：US20230412135A1
公开(公告)日：2023-12-21
申请号：US17843507
申请日：2022-06-17
Applicant: Apple Inc.
Inventor： Kefei Wu , Morteza Nick , David M Signoff , Preeti S Mulage
CPC classification number: H03G3/3026 , H03F3/72 , H04B1/0053 , H03F2200/24 , H03G2201/103
Abstract: This disclosure is directed to reducing output voltage distortions of Variable Gain Amplifiers (VGAs). A VGA may include a number of amplifiers each providing a portion of a total gain of the VGA. For example, a processing circuit may select one or more of the amplifiers of the VGA to provide the output signal with a selected gain. However, the selected amplifiers may provide amplified signals with one or more distortion signals when receiving a bias voltage. Systems and methods are described to reduce or cancel the distortion signals of the selected amplifiers by providing a subthreshold nonzero bias voltage (e.g., a weak voltage) to the remaining (e.g., non-selected) amplifiers of the VGA. For example, the non-selected amplifiers may receive the weak voltage to provide distortion signals with similar voltage amplitude and out of phase compared to the distortion signals of the selected amplifiers.
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公开(公告)号：US20240250705A1
公开(公告)日：2024-07-25
申请号：US18158364
申请日：2023-01-23
Applicant: Apple Inc.
Inventor： Woorim Shin , Morteza Nick , David M. Signoff
CPC classification number: H04B1/0458 , H04B1/16 , H04B2001/0408
Abstract: Wireless circuitry can have an antenna coupled to a receiving amplifier. The receiving amplifier may be coupled to a local feedback loop configured to reduce the gain of the receiving amplifier for suppressing the signal power when receiving a large input signal. The local feedback loop can include a detector and a feedback controller. The detector may have an input coupled to the receiving amplifier and can output a detected signal. The feedback controller may receive the detected signal and output a corresponding control signal. The control signal can be used to reduce the gain of the receiving amplifier by adjusting one or more components within or coupled to the receiving amplifier. Suppressing large input signals in this way presents no additional parasitic loading to the downlink path and can thus provide overvoltage protection without degrading receiver performance.
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公开(公告)号：US11368277B1
公开(公告)日：2022-06-21
申请号：US17236522
申请日：2021-04-21
Applicant: Apple Inc.
Abstract: Embodiments disclosed herein relate to improving a power output of a transmitter of an electronic device. To do so, the transmitter may include signal selection circuitry to adjust a sign selection signal to accurately transition between polarities of a quadrature (e.g., I or Q) component signal stored in or for which an indication is stored in a storage cell of a radio frequency digital-to-analog converter. The sign selection signal may generate a separate adjusted sign selection signal for each polarity of each quadrature component signal such that a transition of the selection signal between a first value and a second value (e.g., logic high and low) occurs when the respective quadrature (e.g., +/− and I/Q component signal is a logic low. In this way, the signal selection circuitry reduces an error pulse in the output of the transmitter.
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公开(公告)号：US10707813B2
公开(公告)日：2020-07-07
申请号：US16212656
申请日：2018-12-06
Applicant: Apple Inc.
Inventor： David M. Signoff , Morteza Nick , Anuranjan Jha
Abstract: A power amplifier and method for operating the same is disclosed. The amplifier includes a number of transistors coupled in series between a power node and a ground node. These transistors include a first transistor having a source terminal coupled to the power node, and a second transistor having its source terminal coupled to a ground node. A subset of transistors is also coupled in series between the first and second transistors. During operation in a first mode, the first and second transistors act as switching transistors, switching according to data received thereby. The subset of transistors, during the first mode, act as cascode transistors. During a second mode of operation, the transistors of the subset act as switching transistors, switching in accordance with the received data.
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Patent Agency Ranking
公开(公告)号：US20240250604A1
公开(公告)日：2024-07-25
申请号：US18099674
申请日：2023-01-20
Applicant: Apple Inc.
Inventor： David M. Signoff , Fei Wang , Kefei Wu , Song Hu , Morteza Nick , Xiang Guan
Abstract: Radio frequency (RF) transmitters of a device (aggressor device) may unintentionally transmit a high-power output signal to antennas of a receiving device (victim device). In some RF systems, a victim device may have no or little protection between its antennas and transistors in an integrated circuit. Performance or lifetime of the transistors may be negatively impacted due to large voltage swings that may result from the high-power signal received from the aggressor device. To prevent or mitigate impact to performance or lifetime of the transistors due to the large voltage swings, protection circuitry including switches and a direct current (DC) power source (e.g., a charge pump) may be implemented at an input of a receiver of the victim device to shunt the power from sensitive circuit components of the victim device.
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公开(公告)号：US11949769B2
公开(公告)日：2024-04-02
申请号：US17734801
申请日：2022-05-02
Applicant: Apple Inc.
CPC classification number: H04L7/0091 , H04L27/04 , H04L27/365 , H03F2200/336
Abstract: Embodiments disclosed herein relate to improving a power output of a transmitter of an electronic device. To do so, the transmitter may include signal selection circuitry to adjust a sign selection signal to accurately transition between polarities of a quadrature (e.g., I or Q) component signal stored in or for which an indication is stored in a storage cell of a radio frequency digital-to-analog converter. The sign selection signal may generate a separate adjusted sign selection signal for each polarity of each quadrature component signal such that a transition of the selection signal between a first value and a second value (e.g., logic high and low) occurs when the respective quadrature (e.g., +/− and I/Q) component signal is a logic low. In this way, the signal selection circuitry reduces an error pulse in the output of the transmitter.
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公开(公告)号：US20240022223A1
公开(公告)日：2024-01-18
申请号：US18476190
申请日：2023-09-27
Applicant: Apple Inc.
Inventor： Kefei Wu , Morteza Nick , David M. Signoff , Preeti S. Mulage
CPC classification number: H03G3/3026 , H03F3/72 , H04B1/0053 , H03G2201/103 , H03F2200/24
Abstract: This disclosure is directed to reducing output voltage distortions of Variable Gain Amplifiers (VGAs). A VGA may include a number of amplifiers each providing a portion of a total gain of the VGA. For example, a processing circuit may select one or more of the amplifiers of the VGA to provide the output signal with a selected gain. However, the selected amplifiers may provide amplified signals with one or more distortion signals when receiving a bias voltage. Systems and methods are described to reduce or cancel the distortion signals of the selected amplifiers by providing a subthreshold nonzero bias voltage (e.g., a weak voltage) to the remaining (e.g., non-selected) amplifiers of the VGA. For example, the non-selected amplifiers may receive the weak voltage to provide distortion signals with similar voltage amplitude and out of phase compared to the distortion signals of the selected amplifiers.
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公开(公告)号：US20220345288A1
公开(公告)日：2022-10-27
申请号：US17734801
申请日：2022-05-02
Applicant: Apple Inc.
Abstract: Embodiments disclosed herein relate to improving a power output of a transmitter of an electronic device. To do so, the transmitter may include signal selection circuitry to adjust a sign selection signal to accurately transition between polarities of a quadrature (e.g., I or Q) component signal stored in or for which an indication is stored in a storage cell of a radio frequency digital-to-analog converter. The sign selection signal may generate a separate adjusted sign selection signal for each polarity of each quadrature component signal such that a transition of the selection signal between a first value and a second value (e.g., logic high and low) occurs when the respective quadrature (e.g., +/− and I/Q) component signal is a logic low. In this way, the signal selection circuitry reduces an error pulse in the output of the transmitter.
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公开(公告)号：US20200186092A1
公开(公告)日：2020-06-11
申请号：US16212656
申请日：2018-12-06
Applicant: Apple Inc.
Inventor： David M. Signoff , Morteza Nick , Anuranjan Jha
Abstract: A power amplifier and method for operating the same is disclosed. The amplifier includes a number of transistors coupled in series between a power node and a ground node. These transistors include a first transistor having a source terminal coupled to the power node, and a second transistor having its source terminal coupled to a ground node. A subset of transistors is also coupled in series between the first and second transistors. During operation in a first mode, the first and second transistors act as switching transistors, switching according to data received thereby. The subset of transistors, during the first mode, act as cascode transistors. During a second mode of operation, the transistors of the subset act as switching transistors, switching in accordance with the received data.
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