公开(公告)号：US12015799B2

公开(公告)日：2024-06-18

申请号：US17589589

申请日：2022-01-31

Applicant: Apple Inc.

Inventor： Sorin C Cismas ,  Ganesh G Yadav

IPC: H04N19/66 ,  H04L65/65 ,  H04L65/70 ,  H04N19/174 ,  H04N19/186

CPC classification number: H04N19/66 ,  H04L65/65 ,  H04L65/70 ,  H04N19/174 ,  H04N19/186

Abstract: This disclosure is directed to systems and methods of data partitioning in image encoding. A video encoder may receive a single stream of video data that includes multiple layers. The video encoder may encode the one or more layers utilizing multiple counters for each component within the layers. The multiple counters may correspond to the header bits, luma bits, and chroma bits within each slice layer. The encoded layers may then be assembled into a single slice before it is sent to a decoder for decoding of image frame.

公开(公告)号：US20240403994A1

公开(公告)日：2024-12-05

申请号：US18510413

申请日：2023-11-15

Applicant: Apple Inc.

Inventor： Sorin C Cismas ,  Alhad A Palkar ,  Kaushik Raghunath ,  Arun Kannan ,  Manjunath M Venkatesh

IPC: G06T1/20 ,  G06T5/00

Abstract: First integrated circuitry including image data rendering circuitry configured to generate image data and memory configured to store a dashboard including dashboard entries indicating a state of the image data to the image data rendering circuitry, wherein the image data rendering circuitry is configured to operate based at least in part on feedback from the dashboard.

公开(公告)号：US20230102584A1

公开(公告)日：2023-03-30

申请号：US17675414

申请日：2022-02-18

Applicant: Apple Inc.

Inventor： Liviu R Morogan ,  Athanasios Leontaris ,  Mark P Rygh ,  Sorin C Cismas

IPC: H04N19/436 ,  H04N19/172 ,  H04N19/423 ,  H04N19/40 ,  H04N19/169 ,  H04N19/186 ,  H04N19/127 ,  H04N19/157

Abstract: The present disclosure relates to systems and methods of multi-processing core processing of image frames during image encoding. The multiple processing cores may be connected via dedicated interfaces and transfer neighbor data between the processing cores to enable parallel processing of frame data. The multiple processing cores may each process quad-rows of image data for a single frame in parallel to reduce memory usage and mitigate latency in video encoding.

公开(公告)号：US12141893B2

公开(公告)日：2024-11-12

申请号：US17933409

申请日：2022-09-19

Applicant: Apple Inc.

Inventor： Ido Y Soffair ,  Uri Nix ,  Yung-Chin Chen ,  Jim C Chou ,  Jian Zhou ,  Assaf Menachem ,  Sorin C Cismas

IPC: G06T1/20 ,  G06T1/60

Abstract: A device may include a display for displaying an image frame based on warped image data and image processing circuitry to generate the warped image data by warping input image data to account for one or more distortions associated with displaying the image. The image processing circuitry may include a two-stage cache architecture having an first cache and an second cache and warp the input image data by generating mapping data indicative of a warp between the input image space and the output image space and fetching the input image data to populate the first cache. Warping may also include populating the second cache with a grouping of pixel values from the first cache that are selected according to a sliding window that traverses the first cache based on the mapping data and interpolating between pixel values of the grouping to generate pixel values of the warped image data.

公开(公告)号：US12075074B2

公开(公告)日：2024-08-27

申请号：US17675414

申请日：2022-02-18

Applicant: Apple Inc.

Inventor： Liviu R Morogan ,  Athanasios Leontaris ,  Mark P Rygh ,  Sorin C Cismas

IPC: H04N19/436 ,  H04N19/127 ,  H04N19/157 ,  H04N19/169 ,  H04N19/172 ,  H04N19/186 ,  H04N19/40 ,  H04N19/423

CPC classification number: H04N19/436 ,  H04N19/127 ,  H04N19/157 ,  H04N19/172 ,  H04N19/186 ,  H04N19/1883 ,  H04N19/40 ,  H04N19/423

Abstract: The present disclosure relates to systems and methods of multi-processing core processing of image frames during image encoding. The multiple processing cores may be connected via dedicated interfaces and transfer neighbor data between the processing cores to enable parallel processing of frame data. The multiple processing cores may each process quad-rows of image data for a single frame in parallel to reduce memory usage and mitigate latency in video encoding.

公开(公告)号：US12015801B2

公开(公告)日：2024-06-18

申请号：US17589641

申请日：2022-01-31

Applicant: Apple Inc.

Inventor： Sorin C Cismas ,  Ganesh G Yadav

IPC: H04N19/70 ,  H04N19/174 ,  H04N19/184 ,  H04N19/186

CPC classification number: H04N19/70 ,  H04N19/174 ,  H04N19/184 ,  H04N19/186

Abstract: This disclosure is directed to systems and methods of streaming extensions for video encoding. The streaming extensions may enable the bitstream syntax for layered video data to be modified to reduce overhead for encoding. The bitstream syntax may be modified to enable variable length luma and chroma components, and enable the alignment between the layers and slice to be bit aligned to enable increased granularity in image encoding, and to minimize overhead between different elements within the layers.

公开(公告)号：US20240095871A1

公开(公告)日：2024-03-21

申请号：US17933409

申请日：2022-09-19

Applicant: Apple Inc.

Inventor： Ido Y Soffair ,  Uri Nix ,  Yung-Chin Chen ,  Jim C Chou ,  Jian Zhou ,  Assaf Menachem ,  Sorin C Cismas

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20

Abstract: A device may include a display for displaying an image frame based on warped image data and image processing circuitry to generate the warped image data by warping input image data to account for one or more distortions associated with displaying the image. The image processing circuitry may include a two-stage cache architecture having an first cache and an second cache and warp the input image data by generating mapping data indicative of a warp between the input image space and the output image space and fetching the input image data to populate the first cache. Warping may also include populating the second cache with a grouping of pixel values from the first cache that are selected according to a sliding window that traverses the first cache based on the mapping data and interpolating between pixel values of the grouping to generate pixel values of the warped image data.

公开(公告)号：US11871003B2

公开(公告)日：2024-01-09

申请号：US17589642

申请日：2022-01-31

Applicant: Apple Inc.

Inventor： Sorin C Cismas ,  Ganesh G Yadav

IPC: H04N19/14 ,  H04N19/174 ,  H04N19/186 ,  H04N19/149 ,  H04N19/30

CPC classification number: H04N19/149 ,  H04N19/14 ,  H04N19/174 ,  H04N19/186 ,  H04N19/30

Abstract: This disclosure is directed to systems and methods of rate control in multiple pass video encoding. The video encoder may complete multiple encoding passes for slices of an image. Rate control algorithms may be implemented that scale the quantization step size and quantization matrix values depending on the determined size of the image slices. This may enable the size of slices to be adjusted based on size parameters for the image data.