公开(公告)号：US12204287B2

公开(公告)日：2025-01-21

申请号：US17816894

申请日：2022-08-02

Applicant: Apple Inc.

Inventor： Bo Zhao ,  Joao Pedro da Silva Cerqueira ,  Pangjie Xu ,  Steven Lu

IPC: H03M1/50 ,  G01R19/255 ,  G04F10/00 ,  H03M1/08

Abstract: A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal.

公开(公告)号：US20240045382A1

公开(公告)日：2024-02-08

申请号：US17816894

申请日：2022-08-02

Applicant: Apple Inc.

Inventor： Bo Zhao ,  Joao Pedro da Silva Cerqueira ,  Pangjie Xu ,  Steven Lu

IPC: G04F10/00 ,  G01R19/255

CPC classification number: G04F10/005 ,  G01R19/255

Abstract: A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal

公开(公告)号：US20250093822A1

公开(公告)日：2025-03-20

申请号：US18955221

申请日：2024-11-21

Applicant: Apple Inc.

Inventor： Bo Zhao ,  Joao Pedro da Silva Cerqueira ,  Pangjie Xu ,  Steven Lu

IPC: G04F10/00 ,  G01R19/255 ,  H03M1/08

Abstract: A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal.