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公开(公告)号：US20250093822A1
公开(公告)日：2025-03-20
申请号：US18955221
申请日：2024-11-21
Applicant: Apple Inc.
Inventor： Bo Zhao , Joao Pedro da Silva Cerqueira , Pangjie Xu , Steven Lu
IPC: G04F10/00 , G01R19/255 , H03M1/08
Abstract: A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal.
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公开(公告)号：US12204287B2
公开(公告)日：2025-01-21
申请号：US17816894
申请日：2022-08-02
Applicant: Apple Inc.
Inventor： Bo Zhao , Joao Pedro da Silva Cerqueira , Pangjie Xu , Steven Lu
IPC: H03M1/50 , G01R19/255 , G04F10/00 , H03M1/08
Abstract: A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal.
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公开(公告)号：US11196435B1
公开(公告)日：2021-12-07
申请号：US17014536
申请日：2020-09-08
Applicant: Apple Inc.
Inventor： Pangjie Xu , Jelam K. Parekh , Mohamed H. Abu-Rahma
Abstract: Systems, apparatuses, and methods for implementing an anti-aliasing technique for a time-to-digital converter are described. A pulse generator generates a pulse with a width that is representative of a voltage level of a supply voltage. A buffer chain receives the pulse from the pulse generator. A first sum is calculated by adding together a number of one bits in a first portion of the buffer chain. Also, a second sum is calculated by adding together a number of one bits in a second portion of the buffer chain. Then, a third sum is calculated by adding the first sum to the second sum if the first sum is saturated. Otherwise, the third sum is equal to the first sum if the first sum is not saturated. The third sum is used as a representation of the voltage level of the supply voltage.
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公开(公告)号：US20240045382A1
公开(公告)日：2024-02-08
申请号：US17816894
申请日：2022-08-02
Applicant: Apple Inc.
Inventor： Bo Zhao , Joao Pedro da Silva Cerqueira , Pangjie Xu , Steven Lu
IPC: G04F10/00 , G01R19/255
CPC classification number: G04F10/005 , G01R19/255
Abstract: A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal
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