公开(公告)号：US20240045382A1

公开(公告)日：2024-02-08

申请号：US17816894

申请日：2022-08-02

Applicant: Apple Inc.

Inventor： Bo Zhao ,  Joao Pedro da Silva Cerqueira ,  Pangjie Xu ,  Steven Lu

IPC: G04F10/00 ,  G01R19/255

CPC classification number: G04F10/005 ,  G01R19/255

Abstract: A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal

公开(公告)号：US11493888B2

公开(公告)日：2022-11-08

申请号：US17193959

申请日：2021-03-05

Applicant: Apple Inc.

Inventor： Bo Zhao ,  Jaroslav Raszka

IPC: H03K5/00 ,  G04F10/00 ,  G04F10/06 ,  H03K5/14

Abstract: A delay circuit with multiple dependencies on various environmental parameters is disclosed. The delay circuit is configured to receive an input signal. The delay circuit includes a first circuit configured to generate a first amount of delay, wherein the first amount of delay has a direct relationship to a first environmental parameter. The delay circuit also includes a second circuit configured to generate a second amount of delay such that the second amount of delay has an inverse relationship to a second environmental parameter. The delay circuit is configured to generate a delayed output signal based on the first and second amounts of delay generated by the first and second circuits.

公开(公告)号：US20220283549A1

公开(公告)日：2022-09-08

申请号：US17193959

申请日：2021-03-05

Applicant: Apple Inc.

Inventor： Bo Zhao ,  Jaroslav Raszka

IPC: G04F10/00 ,  H03K5/14 ,  G04F10/06

Abstract: A delay circuit with multiple dependencies on various environmental parameters is disclosed. The delay circuit is configured to receive an input signal. The delay circuit includes a first circuit configured to generate a first amount of delay, wherein the first amount of delay has a direct relationship to a first environmental parameter. The delay circuit also includes a second circuit configured to generate a second amount of delay such that the second amount of delay has an inverse relationship to a second environmental parameter. The delay circuit is configured to generate a delayed output signal based on the first and second amounts of delay generated by the first and second circuits.

公开(公告)号：US12204287B2

公开(公告)日：2025-01-21

申请号：US17816894

申请日：2022-08-02

Applicant: Apple Inc.

Inventor： Bo Zhao ,  Joao Pedro da Silva Cerqueira ,  Pangjie Xu ,  Steven Lu

IPC: H03M1/50 ,  G01R19/255 ,  G04F10/00 ,  H03M1/08

Abstract: A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal.

公开(公告)号：US10340900B2

公开(公告)日：2019-07-02

申请号：US15389332

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Amrinder S. Barn ,  Bo Zhao ,  Michael A. Dreesen

IPC: G11C7/00 ,  H03F3/45 ,  H03K3/00 ,  H03K3/356 ,  H03K19/0175 ,  G11C29/32 ,  G11C7/10

Abstract: In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.

公开(公告)号：US09385723B1

公开(公告)日：2016-07-05

申请号：US14739719

申请日：2015-06-15

Applicant: Apple Inc.

Inventor： Bo Zhao

IPC: H03L5/00 ,  H03K19/0185 ,  H03K3/356 ,  H03K19/003 ,  H03K17/10

CPC classification number: H03K19/018521 ,  H03K3/356113 ,  H03K17/102 ,  H03K19/00315

Abstract: A level shifter that supports wide voltage range operation by adaptively boosting local supply voltage to its input stage. The level shifter may interface an input (low) voltage domain and an output (high) voltage domain. In the level shifter, an input stage may receive an input signal from the input voltage domain, and an output stage may generate an output signal to be sent to the output voltage domain. In the level shifter, the power supply to the low-voltage input stage is automatically and adaptively boosted to effectuate level conversion of the input signal. A boost control signal is generated when the output signal fails to switch or is slow to switch in response to a corresponding switching of the input signal. In this manner, the voltage operating range of the level shifter is increased. Because boosting is engaged only when needed, the level shifter provides efficient operation with self-adaptability.

Abstract translation: 电平移位器通过自适应地将本地电源电压提升到其输入级来支持宽电压范围运行。 电平移位器可以连接输入（低）电压域和输出（高）电压域。 在电平移位器中，输入级可以从输入电压域接收输入信号，并且输出级可以产生要发送到输出电压域的输出信号。 在电平转换器中，低电压输入级的电源自动自适应地升高，以实现输入信号的电平转换。 当输出信号不能切换或响应于输入信号的相应切换而变慢时，产生升压控制信号。 以这种方式，电平移位器的电压工作范围增加。 因为升压仅在需要时进行，所以电平转换器提供了具有自适应性的高效操作。

公开(公告)号：US20180181193A1

公开(公告)日：2018-06-28

申请号：US15389332

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Amrinder S. Barn ,  Bo Zhao ,  Michael A. Dreesen

IPC: G06F1/32 ,  H03K19/0175 ,  H03K3/356 ,  G11C7/10

CPC classification number: H03K3/356104 ,  G11C7/106 ,  G11C29/32 ,  G11C2029/3202 ,  H03K3/356121 ,  H03K19/017509

Abstract: In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.

公开(公告)号：US20250093822A1

公开(公告)日：2025-03-20

申请号：US18955221

申请日：2024-11-21

Applicant: Apple Inc.

Inventor： Bo Zhao ,  Joao Pedro da Silva Cerqueira ,  Pangjie Xu ,  Steven Lu

IPC: G04F10/00 ,  G01R19/255 ,  H03M1/08

Abstract: A multi-chain measurement circuit is disclosed. The measurement circuit includes first and second chains of serially-connected buffer circuits coupled in parallel, each of which propagates an input signal. A set of storage circuits is configured to store logic values generated by the first and second sets of buffer circuits in response to the transitioning of a clock signal. The logic values stored in the storage circuits result in a digital value indicative of a total number of serially-connected storage circuits through which the input signal has propagated at the time of the transition of the operating clock signal.