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    Systems and methods for PLL gain calibration and duty cycle calibration using shared phase detector
    1.
    发明授权
    Systems and methods for PLL gain calibration and duty cycle calibration using shared phase detector 有权

    公开(公告)号：US12119830B2

    公开(公告)日：2024-10-15

    申请号：US18120819

    申请日：2023-03-13

    Applicant: Apple Inc.

    Inventor： Jongmin Park ,  Karim M Megawer ,  Thomas Mayer

    IPC: H03L7/083 ,  H03L7/081 ,  H03L7/195

    CPC classification number: H03L7/083 ,  H03L7/0818 ,  H03L7/195

    Abstract: This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.

    Electronic Devices Having Wireless Transceivers with Reference Clock Selection
    3.
    发明申请
    Electronic Devices Having Wireless Transceivers with Reference Clock Selection 有权

    公开(公告)号：US20240372555A1

    公开(公告)日：2024-11-07

    申请号：US18312393

    申请日：2023-05-04

    Applicant: Apple Inc.

    Inventor： Thomas Mayer ,  Christian Wicpalek ,  Juergen Koechl ,  Jongmin Park

    IPC: H03L7/093 ,  H03L7/099 ,  H04B1/30

    Abstract: An electronic device may include wireless circuitry with first and second mixers on a signal path for converting a signal using first and second clock signals via high side injection (HSI) or low side injection (LSI). A first phase-locked loop (PLL) may generate the first clock signal and a second PLL may generate the second clock signal. A switch may couple the first PLL to a reference oscillator when LSI is used and may couple the first PLL to a third PLL when HSI is used. The third PLL may generate a second reference signal based on a first reference signal from the reference oscillator. The second PLL may generate the second clock signal based on the output of the third PLL. This may serve to may minimize phase noise even as the mixers switch between HSI and LSI.

    Systems and methods for PLL gain calibration
    4.
    发明授权
    Systems and methods for PLL gain calibration 有权

    公开(公告)号：US12132490B2

    公开(公告)日：2024-10-29

    申请号：US18121404

    申请日：2023-03-14

    Applicant: Apple Inc.

    Inventor： Karim M Megawer ,  Jongmin Park ,  Thomas Mayer

    IPC: H03L7/083 ,  H03L7/081 ,  H03L7/195

    CPC classification number: H03L7/083 ,  H03L7/0818 ,  H03L7/195

    Abstract: This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.

    SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION
    5.
    发明公开
    SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION 审中-公开

    公开(公告)号：US20240313789A1

    公开(公告)日：2024-09-19

    申请号：US18121404

    申请日：2023-03-14

    Applicant: Apple Inc.

    Inventor： Karim M. Megawer ,  Jongmin Park ,  Thomas Mayer

    IPC: H03L7/083 ,  H03L7/081 ,  H03L7/195

    CPC classification number: H03L7/083 ,  H03L7/0818 ,  H03L7/195

    Abstract: This disclosure is directed to PLLs, and, in particular, to enhancing PLL performance via gain calibration. PLL loop gain may vary with respect to process, voltage, and temperature (PVT) variation. To control the PLL loop gain, a gain calibration loop may be implemented. However, calibrating the loop gain by directly measuring the loop gain may be disadvantageous. To reduce or eliminate PLL loop gain variation due to PVT variation, a PLL having a loop gain function that is a function of an input phase offset time with a phase noise performance that remains consistent across PVT variations is disclosed. By determining a relationship between PLL loop gain and phase offset, detecting and calibrating phase offset may result in enhanced calibration of the PLL loop gain, while avoiding the additional difficulty and complexity associated with directly measuring loop gain of a PLL.

    SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION AND DUTY CYCLE CALIBRATION USING SHARED PHASE DETECTOR
    6.
    发明公开
    SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION AND DUTY CYCLE CALIBRATION USING SHARED PHASE DETECTOR 审中-公开

    公开(公告)号：US20240313787A1

    公开(公告)日：2024-09-19

    申请号：US18120819

    申请日：2023-03-13

    Applicant: Apple Inc.

    Inventor： Jongmin Park ,  Karim M Megawer ,  Thomas Mayer

    IPC: H03L7/083 ,  H03L7/081 ,  H03L7/195

    CPC classification number: H03L7/083 ,  H03L7/0818 ,  H03L7/195

    Abstract: This disclosure is directed to enhancing PLL performance via gain calibration and duty cycle calibration. It may be desirable to perform loop gain and duty cycle calibration simultaneously. However, doing so may result in prohibitive complexity and/or area/power penalty. To enable loop gain calibration and duty cycle calibration simultaneously, the duty cycle error and the gain error may be detected in the time domain, which may enable duty cycle calibration and loop gain calibration circuitries to share a phase detector. Detecting the duty cycle error and the loop gain error in the time domain may be accomplished by implementing an analog or digital PLL system, wherein the loop gain of the PLL system is a function of the input phase offset time.

    Systems and methods for PLL duty cycle calibration
    8.
    发明授权
    Systems and methods for PLL duty cycle calibration 有权

    公开(公告)号：US12231132B2

    公开(公告)日：2025-02-18

    申请号：US18120838

    申请日：2023-03-13

    Applicant: Apple Inc.

    Inventor： Karim M Megawer ,  Jongmin Park ,  Thomas Mayer

    IPC: H03L7/081 ,  H03K5/156 ,  H03L7/083 ,  H03L7/087

    Abstract: To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, phase offset information may be extracted.

    SYSTEMS AND METHODS FOR PLL DUTY CYCLE CALIBRATION
    9.
    发明公开
    SYSTEMS AND METHODS FOR PLL DUTY CYCLE CALIBRATION 审中-公开

    公开(公告)号：US20240313788A1

    公开(公告)日：2024-09-19

    申请号：US18120838

    申请日：2023-03-13

    Applicant: Apple Inc.

    Inventor： Karim M. Megawer ,  Jongmin Park ,  Thomas Mayer

    IPC: H03L7/083 ,  H03K5/156 ,  H03L7/081

    CPC classification number: H03L7/083 ,  H03K5/1565 ,  H03L7/0818

    Abstract: To enhance phase-locked loop (PLL) performance, PLL duty-cycle calibration may be desirable. In some cases, higher reference clock frequency may assist in reducing phase noise and increasing power efficiency of the PLL. A frequency doubler may increase the PLL reference clock frequency, but the duty cycle error in the clock may result in a spur at a clock frequency offset. Low phase noise PLL architectures may include a static phase offset at the PLL input between the reference path and the feedback path, and the static phase offset may vary with PVT, which may limit the accuracy of duty cycle error detection. Correcting for the static phase offset may cause a disturbance at the PLL output. To address the duty cycle error caused by the higher reference clock frequency, a duty cycle calibration loop may be introduced. For the duty cycle calibration loop, phase offset information may be extracted.

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