公开(公告)号：US20220100666A1

公开(公告)日：2022-03-31

申请号：US17036442

申请日：2020-09-29

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  Chang Joo LEE ,  James David DUNDAS ,  Muhammed Umar FAROOQ

IPC: G06F12/0864 ,  G06F9/38 ,  G06F12/0891

Abstract: A data processing apparatus and a method are disclosed. The data processing apparatus comprising: a prediction cache to store a plurality of prediction entries, each defining an association between a prediction cache lookup address and a predicted behaviour; prediction circuitry to select a prediction entry based on a prediction cache lookup of the prediction cache based on a given prediction cache lookup address and to determine the predicted behaviour associated with the given prediction cache lookup address based on the selected prediction entry; and a candidate prediction buffer to store a plurality of candidate predictions each indicative of a candidate prediction entry to be selected for inclusion in a subsequent prediction cache lookup, wherein the candidate prediction entry is selected in response to a candidate prediction lookup based on a candidate lookup address different to a candidate prediction cache lookup address indicated as associated with a candidate predicted behaviour in the candidate prediction entry.

公开(公告)号：US20240329999A1

公开(公告)日：2024-10-03

申请号：US18129979

申请日：2023-04-03

Applicant: Arm Limited

Inventor： Chang Joo LEE ,  Jason Lee SETTER ,  Julia Kay LANIER ,  Michael Brian SCHINZLER ,  Yasuo ISHII

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3861 ,  G06F9/3802

Abstract: An apparatus is provided for limiting the effective utilisation of an instruction fetch queue. The instruction fetch entries are used to control the prefetching of instructions from memory, such that those instructions are stored in an instruction cache prior to being required by execution circuitry while executing a program. By limiting the effective utilisation of the instruction fetch queue, fewer instructions will be prefetched and fewer instructions will be allocated to the instruction cache, thus causing fewer evictions from the instruction cache. In the event that the instruction fetch entries are for instructions that are unnecessary to the program, the pollution of the instruction cache with these unnecessary instructions can be mitigated.

公开(公告)号：US20220107898A1

公开(公告)日：2022-04-07

申请号：US17060624

申请日：2020-10-01

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  James David DUNDAS ,  Chang Joo LEE ,  Muhammad Umar FAROOQ

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0873 ,  G06F12/121

Abstract: An apparatus comprises first-level and second-level set-associative caches each comprising the same number of sets of cache entries. Indexing circuitry generates, based on a lookup address, a set index identifying which set of the first-level set-associative cache or the second-level set-associative cache is a selected set of cache entries to be looked up for information associated with the lookup address. The indexing circuitry generates the set index using an indexing scheme which maps the lookup address to the same set index for both the first-level set-associative cache and the second-level set-associative cache. This can make migration of cached information between the cache levels more efficient, which can be particularly useful for caches with high access frequency, such as branch target buffers for a branch predictor.

公开(公告)号：US20230195468A1

公开(公告)日：2023-06-22

申请号：US17557583

申请日：2021-12-21

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Guillaume BOLBENES ,  Thibaut Elie LANOIS ,  Vincenzo CONSALES ,  Chang Joo LEE

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/3844 ,  G06F9/3005

Abstract: An apparatus has a fetch queue to identify a sequence of instructions to be fetched for execution and prediction circuitry to predict upcoming control flow and to control which instructions are identified in the fetch queue in dependence on the prediction. The prediction circuitry predicts multi-taken sequences which are sequences of instructions in which control flow is diverted by a first control flow changing instruction to a series of instructions terminating in a second control flow changing instruction that diverts control flow to a target address. The apparatus also has prediction confidence calculation circuitry to calculate confidence levels for respective multi-taken sequences. Each confidence level is indicative of a confidence in an accuracy of prediction of its respective multi-taken sequence. When the confidence level for a particular multi-taken sequence satisfies a prediction confidence condition, the prediction confidence tracking circuitry allows the particular multi-taken sequence to be predicted by the prediction circuitry. The prediction circuitry causes the series of instructions and the target instruction for the particular multi-taken sequence to be identified in the fetch queue when the prediction circuitry predicts the particular multi-taken sequence and further predictions to be made starting from the target address for the particular multi-taken sequence.

公开(公告)号：US20220107901A1

公开(公告)日：2022-04-07

申请号：US17064068

申请日：2020-10-06

Applicant: Arm Limited

Inventor： Yasuo ISHII ,  James David DUNDAS ,  Chang Joo LEE ,  Muhammed Umar FAROOQ

IPC: G06F12/0897 ,  G06F12/0891 ,  G06F12/02

Abstract: First and second-level caches are provided. Cache control circuitry performs a first-level cache lookup of the first-level cache based on a lookup address, to determine whether the first-level cache stores valid cached data corresponding to the lookup address. When lookup hint information associated with the lookup address is available, the cache control circuitry determines based on the lookup hint information whether to activate or deactivate a second-level cache lookup of the second-level cache. The lookup hint information is indicative of whether the second-level cache is predicted to store valid cached data associated with the lookup address. When the second-level cache lookup is activated, the second-level cache lookup of the second-level cache is performed based on the lookup address to determine whether the second-level cache stores valid cached data corresponding to the lookup address.