公开(公告)号：US11280959B2

公开(公告)日：2022-03-22

申请号：US16856387

申请日：2020-04-23

Applicant: Ayar Labs, Inc.

Inventor： Roy Edward Meade ,  Chen Sun ,  Shahab Ardalan ,  John Fini ,  Forrest Sedgwick

IPC: G02B6/13 ,  G02B6/12 ,  H01L21/66 ,  G01M11/00

Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.

公开(公告)号：US20220107463A1

公开(公告)日：2022-04-07

申请号：US17516602

申请日：2021-11-01

Applicant: Ayar Labs, Inc.

Inventor： Shahab Ardalan ,  Michael Davenport ,  Roy Edward Meade

IPC: G02B6/30 ,  H01L21/56 ,  G02B6/122

Abstract: A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.

公开(公告)号：US20200341191A1

公开(公告)日：2020-10-29

申请号：US16856387

申请日：2020-04-23

Applicant: Ayar Labs, Inc.

Inventor： Roy Edward Meade ,  Chen Sun ,  Shahab Ardalan ,  John Fini ,  Forrest Sedgwick

IPC: G02B6/12 ,  H01L21/66 ,  G02B6/13 ,  G01M11/00

Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.

公开(公告)号：US20240061181A1

公开(公告)日：2024-02-22

申请号：US18499093

申请日：2023-10-31

Applicant: Ayar Labs, Inc.

Inventor： Shahab Ardalan ,  Michael Davenport ,  Roy Edward Meade

IPC: G02B6/30 ,  H01L21/56 ,  G02B6/122

CPC classification number: G02B6/30 ,  H01L21/565 ,  G02B6/122 ,  G02B6/428

Abstract: A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.

公开(公告)号：US11822128B2

公开(公告)日：2023-11-21

申请号：US17516602

申请日：2021-11-01

Applicant: Ayar Labs, Inc.

Inventor： Shahab Ardalan ,  Michael Davenport ,  Roy Edward Meade

IPC: G02B6/30 ,  G02B6/122 ,  H01L21/56 ,  G02B6/42

CPC classification number: G02B6/30 ,  G02B6/122 ,  H01L21/565 ,  G02B6/428

Abstract: A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.

公开(公告)号：US11163120B2

公开(公告)日：2021-11-02

申请号：US16685838

申请日：2019-11-15

Applicant: Ayar Labs, Inc.

Inventor： Shahab Ardalan ,  Michael Davenport ,  Roy Edward Meade

IPC: G02B6/30 ,  G02B6/122 ,  H01L21/56 ,  G02B6/42

Abstract: A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.

公开(公告)号：US11867944B2

公开(公告)日：2024-01-09

申请号：US17701072

申请日：2022-03-22

Applicant: Ayar Labs, Inc.

Inventor： Roy Edward Meade ,  Chen Sun ,  Shahab Ardalan ,  John Fini ,  Forrest Sedgwick

IPC: G02B6/13 ,  G02B6/12 ,  H01L21/66 ,  G01M11/00

CPC classification number: G02B6/12004 ,  G01M11/31 ,  G02B6/13 ,  H01L22/20 ,  H01L22/30 ,  G02B2006/12107 ,  G02B2006/12121 ,  G02B2006/12145 ,  G02B2006/12147 ,  G02B2006/12164

Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.

公开(公告)号：US20230224047A1

公开(公告)日：2023-07-13

申请号：US18152461

申请日：2023-01-10

Applicant: Ayar Labs, Inc.

Inventor： Matthew Sysak ,  Chen Sun ,  Shahab Ardalan ,  Daniel Jeong ,  Songtao Liu

IPC: H04B10/80

CPC classification number: H04B10/806

Abstract: An optical power supply includes a plurality of lasers in a laser array. Each of the plurality of lasers is configured to generate a separate beam of continuous wave laser light. The optical power supply includes a temperature sensor that acquires a temperature associated with the laser array. The optical power supply includes a digital controller that receives notification of the temperature from the temperature senor. The optical power supply includes an optical power adjuster controlled by the digital controller. The optical power adjuster adjusts an optical power level of one or more beams of continuous wave laser light generated by the plurality of lasers to produce an optical power encoding that conveys information about the temperature associated with the laser array as acquired by the temperature sensor. An electro-optic chip receives the beams of continuous wave laser light from the optical power supply and decodes the optical power encoding.

公开(公告)号：US20220214497A1

公开(公告)日：2022-07-07

申请号：US17701072

申请日：2022-03-22

Applicant: Ayar Labs, Inc.

Inventor： Roy Edward Meade ,  Chen Sun ,  Shahab Ardalan ,  John Fini ,  Forrest Sedgwick

IPC: G02B6/12 ,  H01L21/66 ,  G02B6/13 ,  G01M11/00

Abstract: An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.

公开(公告)号：US20200158959A1

公开(公告)日：2020-05-21

申请号：US16685838

申请日：2019-11-15

Applicant: Ayar Labs, Inc.

Inventor： Shahab Ardalan ,  Michael Davenport ,  Roy Edward Meade

IPC: G02B6/30 ,  G02B6/122 ,  H01L21/56

Abstract: A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.