公开(公告)号：US20080162517A1

公开(公告)日：2008-07-03

申请号：US11617610

申请日：2006-12-28

申请人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

发明人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

IPC分类号： G06F17/30

CPC分类号： H03M7/3088

摘要： Some aspects of the invention provide methods, systems, and computer program products for creating an in-memory physical dictionary for data compression. To that end, in accordance with aspects of the present invention, a new heuristic is defined for converting each of the plurality of logical nodes into a corresponding physical node forming a plurality of physical nodes; then place each of the physical nodes into the physical dictionary while traversing the dictionary tree in descending visit count order. Each physical node is placed in its nearest ascendant's cache-line with sufficient space. If there is no space in any of the ascendant's cache-line, then the physical node is placed into a new cache-line, unless a pre-defined packing threshold has been reached, in which case the physical node is placed in the first available cache-line.

公开(公告)号：US07460033B2

公开(公告)日：2008-12-02

申请号：US11617610

申请日：2006-12-28

申请人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

发明人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

IPC分类号： H03M7/34

CPC分类号： H03M7/3088

摘要： Some aspects of the invention provide methods for creating an in-memory physical dictionary for data compression. To that end, in accordance with aspects of the present invention, a new heuristic is defined for converting each of the plurality of logical nodes into a corresponding physical node forming a plurality of physical nodes; then place each of the physical nodes into the physical dictionary while traversing the dictionary tree in descending visit count order. Each physical node is placed in its nearest ascendant's cache-line with sufficient space. If there is no space in any of the ascendant's cache-line, then the physical node is placed into a new cache-line, unless a pre-defined packing threshold has been reached, in which case the physical node is placed in the first available cache-line.

摘要翻译： 本发明的一些方面提供了用于创建用于数据压缩的内存中物理字典的方法。 为此，根据本发明的方面，新的启发式被定义为将多个逻辑节点中的每一个转换成形成多个物理节点的对应的物理节点; 然后将每个物理节点放入物理字典，同时以递减的访问次序顺序遍历字典树。 每个物理节点都放置在其最接近的上升缓存行，并具有足够的空间。 如果任何上升缓存行中没有空格，则物理节点将被放置到新的高速缓存行中，除非已达到预定义的打包阈值，在这种情况下，物理节点被置于第一个可用的 缓存线。

公开(公告)号：US07973680B2

公开(公告)日：2011-07-05

申请号：US12172557

申请日：2008-07-14

申请人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

发明人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

IPC分类号： H03M7/34

CPC分类号： H03M7/3088

摘要： A system and computer readable storage medium for creating an in-memory physical dictionary for data compression are provided. A new heuristic is defined for converting each of a plurality of logical nodes into a corresponding physical node forming a plurality of physical nodes. Each of the physical nodes are placed into the physical dictionary while traversing the dictionary tree in descending visit count order. Each physical node is placed in its nearest ascendant's cache-line with sufficient space. If there is no space in any of the ascendant's cache-line, then the physical node is placed into a new cache-line, unless a pre-defined packing threshold has been reached, in which case the physical node is placed in the first available cache-line.

摘要翻译： 提供了一种用于创建用于数据压缩的内存中物理字典的系统和计算机可读存储介质。 定义了一种新的启发式算法，用于将多个逻辑节点中的每一个转换成形成多个物理节点的对应物理节点。 每个物理节点都以递减的访问次序顺序遍历字典树，放入物理字典。 每个物理节点都放置在其最接近的上升缓存行，并具有足够的空间。 如果任何上升缓存行中没有空格，则物理节点将被放置到新的高速缓存行中，除非已达到预定义的打包阈值，在这种情况下，物理节点被置于第一个可用的 缓存线。

公开(公告)号：US20080275897A1

公开(公告)日：2008-11-06

申请号：US12172557

申请日：2008-07-14

申请人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

发明人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

IPC分类号： G06F17/30

CPC分类号： H03M7/3088

摘要： Some aspects of the invention provide methods, systems, and computer program products for creating an in-memory physical dictionary for data compression. To that end, in accordance with aspects of the present invention, a new heuristic is defined for converting each of the plurality of logical nodes into a corresponding physical node forming a plurality of physical nodes; then place each of the physical nodes into the physical dictionary while traversing the dictionary tree in descending visit count order. Each physical node is placed in its nearest ascendant's cache-line with sufficient space. If there is no space in any of the ascendant's cache-line, then the physical node is placed into a new cache-line, unless a pre-defined packing threshold has been reached, in which case the physical node is placed in the first available cache-line.

摘要翻译： 本发明的一些方面提供了用于创建用于数据压缩的内存中物理字典的方法，系统和计算机程序产品。 为此，根据本发明的方面，新的启发式被定义为将多个逻辑节点中的每一个转换成形成多个物理节点的对应的物理节点; 然后将每个物理节点放入物理字典，同时以递减的访问次序顺序遍历字典树。 每个物理节点都放置在其最接近的上升缓存行，并具有足够的空间。 如果任何上升缓存行中没有空格，则物理节点将被放置到新的高速缓存行中，除非已达到预定义的打包阈值，在这种情况下，物理节点被置于第一个可用的 缓存线。

公开(公告)号：US07283072B1

公开(公告)日：2007-10-16

申请号：US11278118

申请日：2006-03-30

申请人： Piotr M. Plachta ,  Wolfram Sauer ,  Balakrishna Raghavendra Iyer ,  Steven Wayne White

发明人： Piotr M. Plachta ,  Wolfram Sauer ,  Balakrishna Raghavendra Iyer ,  Steven Wayne White

IPC分类号： H03M7/00

CPC分类号： H03M7/3088

摘要： Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favours longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.

摘要翻译： 本发明的一些方面提供用于创建静态词典的方法，系统和计算机程序产品，其中优选较长的字节串。 为此，根据本发明的方面，定义新的启发式来代替用于记录数据树中的特定节点被访问次数的上述频率计数度量。 新的启发式是基于对特定字节串的端节点进行访问的次数进行计数，而不会在每次访问这些节点时频繁地在字节串中间存储字符的节点递增计数 。 结果是有利于较长字节串的发生计数度量，偏向于不增加在字节串中间存储字符的节点的相应出现计数值。

公开(公告)号：US08037034B2

公开(公告)日：2011-10-11

申请号：US11781833

申请日：2007-07-23

申请人： Piotr M. Plachta ,  Wolfram Sauer ,  Balakrishna Raghavendra Iyer ,  Steven Wayne White

发明人： Piotr M. Plachta ,  Wolfram Sauer ,  Balakrishna Raghavendra Iyer ,  Steven Wayne White

IPC分类号： G06F7/00 ,  G06F17/00

CPC分类号： H03M7/3088

摘要： Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favors longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.

摘要翻译： 本发明的一些方面提供用于创建静态词典的方法，系统和计算机程序产品，其中优选较长的字节串。 为此，根据本发明的方面，定义新的启发式来代替用于记录数据树中的特定节点被访问次数的上述频率计数度量。 新的启发式是基于对特定字节串的端节点进行访问的次数进行计数，而不会在每次访问这些节点时频繁地在字节串中间存储字符的节点递增计数 。 结果是有利于较长字节串的发生计数度量，偏向于不增加在字节串中间存储字符的节点的相应出现计数值。

公开(公告)号：US07779234B2

公开(公告)日：2010-08-17

申请号：US11877391

申请日：2007-10-23

申请人： James W. Bishop ,  Hung Q. Le ,  Dung Q. Nguyen ,  Wolfram Sauer ,  Benjamin W. Stolt ,  Michael T. Vaden

发明人： James W. Bishop ,  Hung Q. Le ,  Dung Q. Nguyen ,  Wolfram Sauer ,  Benjamin W. Stolt ,  Michael T. Vaden

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/383

摘要： The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread.

摘要翻译： 本发明包括一种用于在微处理器的负载初始化机制下实现硬件支持的线程辅助的系统和方法。 根据本发明的实施例，当微处理器的一个线程处于睡眠模式时，可以激活硬件线程辅助模式。 当加载前瞻模式被激活时，固定点单元将一个或多个架构设施的内容从活动线程复制到第一个非活动线程中的相应的架构设施。 加载存储单元在负载前瞻模式中执行至少一个推测负载，并将至少一个推测负载的结果写入第一非活动线程中的复制架构设施。

公开(公告)号：US20080256345A1

公开(公告)日：2008-10-16

申请号：US11733589

申请日：2007-04-10

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Michael Karl Gschwind ,  Ravi Nair ,  Robert Alan Philhower ,  Wolfram Sauer ,  Raymond Cheung Yeung

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Michael Karl Gschwind ,  Ravi Nair ,  Robert Alan Philhower ,  Wolfram Sauer ,  Raymond Cheung Yeung

IPC分类号： G06F7/38

CPC分类号： G06F9/3844 ,  G06F1/3203 ,  G06F9/3802 ,  G06F9/3806

摘要： An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.

摘要翻译： 一种信息处理系统包括处理器，每当对分支指令队列中存储的分支指令的分支预测中的不准确性或缺乏置信度的不准确性或缺乏置信度超过预定的不准确度或误差的阈值置信水平时，可以节制指令获取器。 以这种方式，当处理器可能会错误地预测分支指令的结果时，获取操作减慢以节省处理器功率。 当处理器可能正确预测分支指令的结果时，获取操作将返回全速。

公开(公告)号：US20070229323A1

公开(公告)日：2007-10-04

申请号：US11278118

申请日：2006-03-30

申请人： Piotr Plachta ,  Wolfram Sauer ,  Balakrishna Iyer ,  Steven White

发明人： Piotr Plachta ,  Wolfram Sauer ,  Balakrishna Iyer ,  Steven White

IPC分类号： H03M7/34

CPC分类号： H03M7/3088

摘要： Some aspects of the invention provide methods, systems, and computer program products for creating a static dictionary in which longer byte-strings are preferred. To that end, in accordance with aspects of the present invention, a new heuristic is defined to replace the aforementioned frequency count metric used to record the number of times a particular node in a data tree is visited. The new heuristic is based on counting the number of times an end-node of a particular byte-string is visited, while not incrementing a count for nodes storing characters in the middle of the byte-string as often as each time such nodes are visited. The result is an occurrence count metric that favours longer byte-strings, by being biased towards not incrementing the respective occurrence count values for nodes storing characters in the middle of a byte-string.

摘要翻译： 本发明的一些方面提供用于创建静态词典的方法，系统和计算机程序产品，其中优选较长的字节串。 为此，根据本发明的方面，定义新的启发式来代替用于记录数据树中的特定节点被访问次数的上述频率计数度量。 新的启发式是基于对特定字节串的端节点进行访问的次数进行计数，而不会在每次访问这些节点时频繁地在字节串中间存储字符的节点递增计数 。 结果是有利于较长字节串的发生计数度量，偏向于不增加在字节串中间存储字符的节点的相应出现计数值。

公开(公告)号：US20060174096A1

公开(公告)日：2006-08-03

申请号：US11049014

申请日：2005-02-02

申请人： Brian Konigsburg ,  David Levitan ,  Wolfram Sauer ,  Samuel Thomas

发明人： Brian Konigsburg ,  David Levitan ,  Wolfram Sauer ,  Samuel Thomas

IPC分类号： G06F9/00

CPC分类号： G06F9/3806

摘要： Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.

摘要翻译： 公开了将分支信息存储在处理器的地址表中的方法和系统。 所公开的实施例的处理器通常可以包括连接到指令高速缓存的指令获取单元，分支执行单元和连接到指令获取单元和分支执行单元的地址表。 地址表通常适于存储多个条目，其中地址表的每个条目适于存储基地址和基本指令标签。 在另一实施例中，分支执行单元可以适于基于与指令标签相关联的地址表的条目的基地址和基本指令标签来确定具有指令标签的分支指令的地址。 在一些实施例中，地址表还可以适于存储分支信息。