公开(公告)号：US20080162517A1

公开(公告)日：2008-07-03

申请号：US11617610

申请日：2006-12-28

申请人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

发明人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

IPC分类号： G06F17/30

CPC分类号： H03M7/3088

摘要： Some aspects of the invention provide methods, systems, and computer program products for creating an in-memory physical dictionary for data compression. To that end, in accordance with aspects of the present invention, a new heuristic is defined for converting each of the plurality of logical nodes into a corresponding physical node forming a plurality of physical nodes; then place each of the physical nodes into the physical dictionary while traversing the dictionary tree in descending visit count order. Each physical node is placed in its nearest ascendant's cache-line with sufficient space. If there is no space in any of the ascendant's cache-line, then the physical node is placed into a new cache-line, unless a pre-defined packing threshold has been reached, in which case the physical node is placed in the first available cache-line.

公开(公告)号：US07973680B2

公开(公告)日：2011-07-05

申请号：US12172557

申请日：2008-07-14

申请人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

发明人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

IPC分类号： H03M7/34

CPC分类号： H03M7/3088

摘要： A system and computer readable storage medium for creating an in-memory physical dictionary for data compression are provided. A new heuristic is defined for converting each of a plurality of logical nodes into a corresponding physical node forming a plurality of physical nodes. Each of the physical nodes are placed into the physical dictionary while traversing the dictionary tree in descending visit count order. Each physical node is placed in its nearest ascendant's cache-line with sufficient space. If there is no space in any of the ascendant's cache-line, then the physical node is placed into a new cache-line, unless a pre-defined packing threshold has been reached, in which case the physical node is placed in the first available cache-line.

摘要翻译： 提供了一种用于创建用于数据压缩的内存中物理字典的系统和计算机可读存储介质。 定义了一种新的启发式算法，用于将多个逻辑节点中的每一个转换成形成多个物理节点的对应物理节点。 每个物理节点都以递减的访问次序顺序遍历字典树，放入物理字典。 每个物理节点都放置在其最接近的上升缓存行，并具有足够的空间。 如果任何上升缓存行中没有空格，则物理节点将被放置到新的高速缓存行中，除非已达到预定义的打包阈值，在这种情况下，物理节点被置于第一个可用的 缓存线。

公开(公告)号：US20080275897A1

公开(公告)日：2008-11-06

申请号：US12172557

申请日：2008-07-14

申请人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

发明人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

IPC分类号： G06F17/30

CPC分类号： H03M7/3088

摘要： Some aspects of the invention provide methods, systems, and computer program products for creating an in-memory physical dictionary for data compression. To that end, in accordance with aspects of the present invention, a new heuristic is defined for converting each of the plurality of logical nodes into a corresponding physical node forming a plurality of physical nodes; then place each of the physical nodes into the physical dictionary while traversing the dictionary tree in descending visit count order. Each physical node is placed in its nearest ascendant's cache-line with sufficient space. If there is no space in any of the ascendant's cache-line, then the physical node is placed into a new cache-line, unless a pre-defined packing threshold has been reached, in which case the physical node is placed in the first available cache-line.

摘要翻译： 本发明的一些方面提供了用于创建用于数据压缩的内存中物理字典的方法，系统和计算机程序产品。 为此，根据本发明的方面，新的启发式被定义为将多个逻辑节点中的每一个转换成形成多个物理节点的对应的物理节点; 然后将每个物理节点放入物理字典，同时以递减的访问次序顺序遍历字典树。 每个物理节点都放置在其最接近的上升缓存行，并具有足够的空间。 如果任何上升缓存行中没有空格，则物理节点将被放置到新的高速缓存行中，除非已达到预定义的打包阈值，在这种情况下，物理节点被置于第一个可用的 缓存线。

公开(公告)号：US07460033B2

公开(公告)日：2008-12-02

申请号：US11617610

申请日：2006-12-28

申请人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

发明人： Balakrishna Raghavendra Iyer ,  Piotr M. Plachta ,  Wolfram Sauer ,  Steven W. White

IPC分类号： H03M7/34

CPC分类号： H03M7/3088

摘要： Some aspects of the invention provide methods for creating an in-memory physical dictionary for data compression. To that end, in accordance with aspects of the present invention, a new heuristic is defined for converting each of the plurality of logical nodes into a corresponding physical node forming a plurality of physical nodes; then place each of the physical nodes into the physical dictionary while traversing the dictionary tree in descending visit count order. Each physical node is placed in its nearest ascendant's cache-line with sufficient space. If there is no space in any of the ascendant's cache-line, then the physical node is placed into a new cache-line, unless a pre-defined packing threshold has been reached, in which case the physical node is placed in the first available cache-line.

摘要翻译： 本发明的一些方面提供了用于创建用于数据压缩的内存中物理字典的方法。 为此，根据本发明的方面，新的启发式被定义为将多个逻辑节点中的每一个转换成形成多个物理节点的对应的物理节点; 然后将每个物理节点放入物理字典，同时以递减的访问次序顺序遍历字典树。 每个物理节点都放置在其最接近的上升缓存行，并具有足够的空间。 如果任何上升缓存行中没有空格，则物理节点将被放置到新的高速缓存行中，除非已达到预定义的打包阈值，在这种情况下，物理节点被置于第一个可用的 缓存线。

公开(公告)号：US5796998A

公开(公告)日：1998-08-18

申请号：US754377

申请日：1996-11-21

申请人： David Stephen Levitan ,  John S. Muhich ,  Adam R. Talcott ,  Steven W. White

发明人： David Stephen Levitan ,  John S. Muhich ,  Adam R. Talcott ,  Steven W. White

IPC分类号： G06F9/38 ,  G06F9/32

CPC分类号： G06F9/3806 ,  G06F9/327 ,  G06F9/3804 ,  G06F9/3851

摘要： An apparatus and method for fetching instructions in an information handling system operating at a predetermined number of cycles per second includes an instruction cache for storing instructions to be fetched. Branch target calculators are operably coupled to instruction queues and to a fetch address selector for determining, in parallel, if instructions in the instruction queues are branch instructions and for providing, in parallel, a target address for each of the instruction queues to the fetch address selector such that the fetch address selector can provide the instruction cache with one of the plurality of target addresses as the next fetch address. Decoding of instructions, calculating the target addresses of branch instructions, and resolving branch instructions are performed in parallel instead of sequentially and, in this manner, back-to-back taken branches can be executed at a rate of one per cycle.

摘要翻译： 用于在以每秒预定的周期数工作的信息处理系统中取指令的装置和方法包括用于存储要获取的指令的指令高速缓存。 分支目标计算器可操作地耦合到指令队列和提取地址选择器，用于并行地确定如果指令队列中的指令是分支指令并且用于并行地提供每个指令队列到获取地址的目标地址 选择器使得提取地址选择器可以将指令高速缓存与多个目标地址中的一个提供为下一个提取地址。 执行指令解码，计算分支指令的目标地址和解析分支指令，而不是依次执行，并且以这种方式，可以以每个周期一个速率执行背对背拍摄的分支。

公开(公告)号：US06907509B2

公开(公告)日：2005-06-14

申请号：US10298483

申请日：2002-11-18

申请人： Brian C. Hall ,  Robert J. Blainey ,  Steven W. White

发明人： Brian C. Hall ,  Robert J. Blainey ,  Steven W. White

IPC分类号： G06F9/00 ,  G06F9/45 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F8/4442

摘要： A method, a computer or computer program product for automatically restructuring a program having arrays in inner loops to reduce an average penalty incurred for bursty cache miss patterns by spreading out the cache misses. The method may be used separately or in conjunction with methods for reducing the number of cache misses. The method determines a padding required for each array according to a proportion of the cache line size, to offset the starting points of the arrays relative to the start of a cache line memory access address for each array. Preferably, the starting points of the arrays that induce bursty cache misses are padded so that they are uniformly spaced from one another.

摘要翻译： 一种用于在内循环中自动重组具有阵列的程序的方法，计算机或计算机程序产品，以通过扩展高速缓存未命中来减少突发高速缓存未命中模式造成的平均损失。 该方法可以单独使用或与减少高速缓存未命中数量的方法结合使用。 该方法根据高速缓存行大小的比例来确定每个阵列所需的填充，以相对于每个阵列的高速缓存行存储器访问地址的开始偏移数组的起始点。 优选地，引发突发高速缓存未命中的阵列的起始点被填充，使得它们彼此均匀间隔开。

公开(公告)号：US20130013705A1

公开(公告)日：2013-01-10

申请号：US13544814

申请日：2012-07-09

申请人： Steven W. White ,  Ashok Ramadass

发明人： Steven W. White ,  Ashok Ramadass

IPC分类号： G06F15/16

CPC分类号： H04L63/0245 ,  G06F21/6218 ,  G06F2221/2101 ,  G06F2221/2149

摘要： A method for filtering content with a communication device includes, with the communication device, applying a filter function to a message associated with the communication device, the filter function finding at least one content element. The method further includes comparing the content element with a set of restricted content elements, and withholding the message from communication in response to determining that the content element matches one of the restricted content elements.

摘要翻译： 用通信设备过滤内容的方法包括与通信设备一起对与通信设备相关联的消息应用过滤器功能，所述过滤器功能查找至少一个内容元素。 该方法还包括将内容元素与一组受限内容元素进行比较，并响应于确定内容元素与受限内容元素中的一个相匹配而将该消息从通信中扣留。

公开(公告)号：US5357618A

公开(公告)日：1994-10-18

申请号：US686221

申请日：1991-04-15

申请人： Jamshed H. Mirza ,  Steven W. White

发明人： Jamshed H. Mirza ,  Steven W. White

IPC分类号： G06F9/32 ,  G06F9/312 ,  G06F9/345 ,  G06F9/38 ,  G06F12/08 ,  G06F13/14

CPC分类号： G06F9/30043 ,  G06F12/0862 ,  G06F9/30032 ,  G06F9/3013 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6026 ,  G06F2212/6028 ,  G06F8/4442

摘要： A technique and a mechanism accurately determines the correct prefetch line for loops with strides of 1, N, or a combination of stride values. Stride registers are used to assist in prefetching. Furthermore, stride register values can be used to specify "cacheability" of data on an object by object basis to prevent "cache flushing". The compiler uses a new instruction, "MOVE GPR TO STRIDE REGISTER", prior to a loop to insert the "calculated stride value(s)" into the stride register(s) associated with the index register(s) which will be incremented by that stride value. At the end of the loop, a second new instruction, "CLEAR STRIDE REGISTER SET", is used to place a value of zero in all of the stride registers to inhibit prefetching of data which would most likely not be used. A zero value in the stride registers inhibits prefetching. Non-zero values in the stride registers clearly mark the execution of a loop, which is where prefetching makes the most sense. It also clearly indicates the correct offset from the current address to use in determining the prefetch address. Since the offset is dependent on the particular index register used in specifying the storage address, data for loops with multiple strides can be correctly prefetched. A hardware managed set of stride registers provides a subset of the benefits afforded by the software managed implementation.

摘要翻译： 技术和机制准确地确定了具有1，N的步幅或步幅值的组合的循环的正确预取行。 Stride寄存器用于辅助预取。 此外，可以使用步幅寄存器值来指定对象上的数据的“缓存”，以防止“缓存刷新”。 在循环之前，编译器使用新的指令“MOVE GPR TO STRIDE REGISTER”，将“计算出的步幅值”插入到与索引寄存器相关联的步幅寄存器中，该寄存器将被递增 那一步的价值。 在循环结束时，第二个新指令“CLEAR STRIDE REGISTER SET”用于在所有的步幅寄存器中设置一个零值，以禁止最可能不使用的数据预取。 步幅寄存器中的零值禁止预取。 步进寄存器中的非零值清楚地标记循环的执行，这是预取最有意义的地方。 它还清楚地指出了与确定预取地址时使用的当前地址的正确偏移。 由于偏移取决于用于指定存储地址的特定索引寄存器，因此可以正确预取具有多个步长的循环的数据。 硬件管理的步进寄存器集提供了软件管理实现提供的一些优点。

公开(公告)号：US5348711A

公开(公告)日：1994-09-20

申请号：US95321

申请日：1993-07-21

申请人： Kenneth A. Johnson ,  Steven W. White

发明人： Kenneth A. Johnson ,  Steven W. White

IPC分类号： A61L2/20 ,  A61L2/00 ,  A61L9/00

CPC分类号： A61L2/20

摘要： A dental handpiece sterilizer includes a sterilization chamber with an internal manifold system having outlet connectors into which dental handpieces can be plugged. A sterilant vapor introduced to the manifold flows through the dental handpieces coupled to the manifold and into the interior of the chamber so that it contacts the exterior surfaces of the handpieces before exiting the sterilant chamber.

摘要翻译： 牙科手机消毒器包括具有内部歧管系统的消毒室，其具有可插入牙科手机的出口连接器。 引入到歧管的灭菌剂蒸汽流过耦合到歧管并进入腔室内部的牙科手柄，使得它在离开灭菌室之前接触手机的外表面。

公开(公告)号：US5058003A

公开(公告)日：1991-10-15

申请号：US285176

申请日：1988-12-15

申请人： Steven W. White

发明人： Steven W. White

IPC分类号： G06F12/10

CPC分类号： G06F12/1036 ,  G06F2212/652

摘要： A dynamic address translation mechanism includes a first directory-look-aside-table (DLAT) for 4KB page sizes and a second DLAT for 1MB page sizes. The page size does need not be known prior to DLAT presentation. When a virtual address is presented for translation, it is applied simultaneously to both DLATs for translation by either DLAT if it contains a page address entry corresponding to the virtual address presented. If a DLAT "miss" occurs, segment/page table searching is initiated. The DLAT page sizes are preferably made equal to the segment/page sizes and placed on 4KB and 1MB boundaries. Virtual page addresses lie within either a 1MB page or a 4KB page, and an entry for any virtual address can exist in only one (not both) of the DLATs.