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1.发明授权Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling system 失效当处理器在信息处理系统中遇到低置信度分支时，通过节流指令获取来节省功率的方法和装置公开(公告)号：US07627742B2
公开(公告)日：2009-12-01
申请号：US11733589
申请日：2007-04-10
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
IPC分类号： G06F1/32
CPC分类号： G06F9/3844 , G06F1/3203 , G06F9/3802 , G06F9/3806
摘要： An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.
摘要翻译： 一种信息处理系统包括处理器，每当对分支指令队列中存储的分支指令的分支预测中的不准确性或缺乏置信度的不准确性或缺乏置信度超过预定的不准确度或误差的阈值置信水平时，可以节制指令获取器。 以这种方式，当处理器可能会错误地预测分支指令的结果时，获取操作减慢以节省处理器功率。 当处理器可能正确预测分支指令的结果时，获取操作将返回全速。
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2.发明申请Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System 失效当处理器在信息处理系统中遇到低置信度时通过调节指令获取来节省电力的方法和装置公开(公告)号：US20080256345A1
公开(公告)日：2008-10-16
申请号：US11733589
申请日：2007-04-10
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Michael Karl Gschwind , Ravi Nair , Robert Alan Philhower , Wolfram Sauer , Raymond Cheung Yeung
IPC分类号： G06F7/38
CPC分类号： G06F9/3844 , G06F1/3203 , G06F9/3802 , G06F9/3806
摘要： An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions.
摘要翻译： 一种信息处理系统包括处理器，每当对分支指令队列中存储的分支指令的分支预测中的不准确性或缺乏置信度的不准确性或缺乏置信度超过预定的不准确度或误差的阈值置信水平时，可以节制指令获取器。 以这种方式，当处理器可能会错误地预测分支指令的结果时，获取操作减慢以节省处理器功率。 当处理器可能正确预测分支指令的结果时，获取操作将返回全速。
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3.发明授权Method and system for controlling power in a chip through a power-performance monitor and control unit 有权通过功率监控和控制单元控制芯片功率的方法和系统公开(公告)号：US07421601B2
公开(公告)日：2008-09-02
申请号：US11357612
申请日：2006-02-17
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchical architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每个层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，而较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。
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4.发明申请Method and system for controlling power in a chip through a power-performance monitor and control unit 有权通过功率监控和控制单元控制芯片功率的方法和系统公开(公告)号：US20070198863A1
公开(公告)日：2007-08-23
申请号：US11357612
申请日：2006-02-17
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。
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5.发明授权Method and system of peak power enforcement via autonomous token-based control and management 有权通过自主的基于令牌的控制和管理来实现峰值功率的方法和系统公开(公告)号：US07930578B2
公开(公告)日：2011-04-19
申请号：US11862559
申请日：2007-09-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
CPC分类号： G06F1/3287 , G06F1/206 , G06F9/3836 , G06F9/3869 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D50/20
摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.
摘要翻译： 一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令 状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间 间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率 基于系统中分配的令牌总数的消耗限制。
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6.发明申请METHOD AND SYSTEM OF PEAK POWER ENFORCEMENT VIA AUTONOMOUS TOKEN-BASED CONTROL AND MANAGEMENT 有权通过自动基于方法的控制和管理，峰值功率执行的方法和系统公开(公告)号：US20090089602A1
公开(公告)日：2009-04-02
申请号：US11862559
申请日：2007-09-27
申请人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
发明人： Pradip Bose , Alper Buyuktosunoglu , Chen-Yong Cher , Zhigang Hu , Hans Jacobson , Prabhakar N. Kudva , Vijayalakshmi Srinivasan , Victor Zyuban
IPC分类号： G06F1/28
CPC分类号： G06F1/3287 , G06F1/206 , G06F9/3836 , G06F9/3869 , G06F9/5094 , Y02D10/16 , Y02D10/171 , Y02D10/22 , Y02D50/20
摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.
摘要翻译： 一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令 状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间 间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率 基于系统中分配的令牌总数的消耗限制。
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7.发明申请METHOD AND SYSTEM FOR CONTROLLING POWER IN A CHIP THROUGH A POWER-PERFORMANCE MONITOR AND CONTROL UNIT 失效通过功率性能监视器和控制单元控制芯片中的功率的方法和系统公开(公告)号：US20090049318A1
公开(公告)日：2009-02-19
申请号：US12132044
申请日：2008-06-03
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。
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8.发明授权Method and system for controlling power in a chip through a power performance monitor and control unit 有权通过功率性能监测和控制单元控制芯片功率的方法和系统公开(公告)号：US08639955B2
公开(公告)日：2014-01-28
申请号：US13292712
申请日：2011-11-09
IPC分类号： G06F1/00
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。
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9.发明授权Method and system for controlling power in a chip through a power-performance monitor and control unit 失效通过功率监控和控制单元控制芯片功率的方法和系统公开(公告)号：US08112642B2
公开(公告)日：2012-02-07
申请号：US12132044
申请日：2008-06-03
CPC分类号： G06F1/206 , G06F1/3203 , Y02D10/16
摘要： A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchal architecture is responsive to commands from a higher level, and the commands provide instructions on operations and power distribution, such that the higher levels provide modes of operation and budgets to lower levels and the lower levels provide feedback to the higher levels to control and manage power usage in the microprocessor system both globally and locally.
摘要翻译： 用于控制微处理器系统中的功率和性能的系统和方法包括集成到微处理器系统中的监视和控制系统。 监视和控制系统包括具有多个层的层次结构。 层次结构中的每层都响应来自更高级别的命令，并且命令提供关于操作和功率分配的指令，使得较高级别提供操作模式和预算以降低级别，并且较低级别向较高级别提供反馈 在全球和本地控制和管理微处理器系统中的电力使用。
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10.发明申请ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS 有权基于自适应工作负载的优化与异构电流基准设计相结合，以减轻集成电路中的电流传输限制公开(公告)号：US20140195996A1
公开(公告)日：2014-07-10
申请号：US13526252
申请日：2012-06-18
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036
摘要： A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.
摘要翻译： 与“前置硅”设计方法和“后硅”当前优化编程方法相结合的动态系统，以改进和优化当前传输到芯片的传输，这受到连接的物理特性的限制（例如，受控崩溃芯片连接或 C4s）。 该机制包括测量或估计芯片内特定粒度的功耗，使用一种方法将功率信息转换为C4当前信息，并在适用的情况下触发限流机制（包括基于令牌的限制），以限制每个C4超过预先的当前传输 - 建立的限制或期限。 设计辅助工具用于根据当前交付要求在整个芯片上分配C4。 该系统与设计和编程方法相结合，改进并优化电流传递可扩展到多层3D芯片堆叠中的层间连接。
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