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    Synchronous serial display monitor control and communications bus interface
    2.
    发明授权
    Synchronous serial display monitor control and communications bus interface 失效
    同步串行显示监控和通讯总线接口

    公开(公告)号：US6057860A

    公开(公告)日：2000-05-02

    申请号：US632754

    申请日：1996-04-16

    申请人： Bradley W. Hoffert ,  Shawn F. Storm ,  Abraham E. Rindal ,  Kenneth A. Gross ,  Robert Stano

    发明人： Bradley W. Hoffert ,  Shawn F. Storm ,  Abraham E. Rindal ,  Kenneth A. Gross ,  Robert Stano

    IPC分类号： G06F13/42 ,  G09G1/16 ,  G06F13/14

    CPC分类号： G09G1/167 ,  G06F13/4291 ,  G09G2370/045

    摘要： A monitor interface cable for transmitting display data and command data between a computer system and a display monitor preferably including a microcontroller. The monitor interface cable enables both display and command data to be transmitted simultaneously from the computer system to the display monitor. Inside the computer system, data containing the commands written to a particular memory location in a video buffer card is applied to various signal lines located in the monitor interface cable. These signal lines are coupled to the microcontroller located in the display monitor which receives the commands and performs various controlling functions in response. Status information in the form of a command is transmitted back across a second signal line to the computer system where various software programs including drivers receive and process the status information. Display data is simultaneously transmitted over other signal lines also located in the monitor interface cable.

    摘要翻译： 一种用于在计算机系统和显示监视器之间发送显示数据和命令数据的监视器接口电缆，优选地包括微控制器。 监视器接口电缆使显示和命令数据能够从计算机系统同时传输到显示监视器。 在计算机系统内，包含写入视频缓冲卡中的特定存储器位置的命令的数据被应用于位于监视器接口电缆中的各种信号线。 这些信号线耦合到位于显示监视器中的微控制器，其接收命令并且执行各种控制功能作为响应。 以命令形式的状态信息通过第二信号线传送到计算机系统，其中包括驱动程序的各种软件程序接收和处理状态信息。 显示数据同时通过位于监视器接口电缆中的其他信号线传输。

    Bus architecture for integrated data and video memory
    6.
    发明授权
    Bus architecture for integrated data and video memory 失效
    集成数据和视频存储器的总线架构

    公开(公告)号：US5265218A

    公开(公告)日：1993-11-23

    申请号：US886671

    申请日：1992-05-19

    申请人： James Testa ,  Andreas Behtolsheim ,  Edward Frank ,  Trevor Creary ,  David Emberson ,  Shawn F. Storm ,  Bradley Hoffert

    发明人： James Testa ,  Andreas Behtolsheim ,  Edward Frank ,  Trevor Creary ,  David Emberson ,  Shawn F. Storm ,  Bradley Hoffert

    IPC分类号： G06F13/16 ,  G06F13/42

    CPC分类号： G06F13/4243 ,  G06F13/1663

    摘要： A bus architecture and protocol for integrated data and video memory. A high speed dedicated memory bus is coupled to a memory controller. The memory controller is in turn coupled to a multiple processor bus interconnecting one or more processors. Single in-line memory modules (SIMMs) incorporating dynamic random access memory (DRAM), video RAM (VRAM), and static nonvolatile RAM (SRAM) are coupled to the memory bus. Bus control signals forming a bus protocol, and address and data lines from the memory controller are shared by all memory modules operating on the memory bus. Certain control signals invoke specific operations on memory modules or are ignored, depending on the type of memory module receiving the control signal. The memory modules incorporate the consistent protocol by virtue of a consistent control signal pin out. The SIMMs further incorporate buffering and conversion functions, thereby relieving the memory controller of service overhead associated with these functions. Integrating all forms of memory into a single data and video memory architecture permits a highly functional dedicated memory bus to be connected to the computer system.