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    Synchronous serial display monitor control and communications bus interface
    2.
    发明授权
    Synchronous serial display monitor control and communications bus interface 失效
    同步串行显示监控和通讯总线接口

    公开(公告)号：US6057860A

    公开(公告)日：2000-05-02

    申请号：US632754

    申请日：1996-04-16

    申请人： Bradley W. Hoffert ,  Shawn F. Storm ,  Abraham E. Rindal ,  Kenneth A. Gross ,  Robert Stano

    发明人： Bradley W. Hoffert ,  Shawn F. Storm ,  Abraham E. Rindal ,  Kenneth A. Gross ,  Robert Stano

    IPC分类号： G06F13/42 ,  G09G1/16 ,  G06F13/14

    CPC分类号： G09G1/167 ,  G06F13/4291 ,  G09G2370/045

    摘要： A monitor interface cable for transmitting display data and command data between a computer system and a display monitor preferably including a microcontroller. The monitor interface cable enables both display and command data to be transmitted simultaneously from the computer system to the display monitor. Inside the computer system, data containing the commands written to a particular memory location in a video buffer card is applied to various signal lines located in the monitor interface cable. These signal lines are coupled to the microcontroller located in the display monitor which receives the commands and performs various controlling functions in response. Status information in the form of a command is transmitted back across a second signal line to the computer system where various software programs including drivers receive and process the status information. Display data is simultaneously transmitted over other signal lines also located in the monitor interface cable.

    摘要翻译： 一种用于在计算机系统和显示监视器之间发送显示数据和命令数据的监视器接口电缆，优选地包括微控制器。 监视器接口电缆使显示和命令数据能够从计算机系统同时传输到显示监视器。 在计算机系统内，包含写入视频缓冲卡中的特定存储器位置的命令的数据被应用于位于监视器接口电缆中的各种信号线。 这些信号线耦合到位于显示监视器中的微控制器，其接收命令并且执行各种控制功能作为响应。 以命令形式的状态信息通过第二信号线传送到计算机系统，其中包括驱动程序的各种软件程序接收和处理状态信息。 显示数据同时通过位于监视器接口电缆中的其他信号线传输。

    Memory controller for controlling different memory types and generating uncorrectable error faults when an access operation is performed to a wrong type
    9.
    发明授权
    Memory controller for controlling different memory types and generating uncorrectable error faults when an access operation is performed to a wrong type 失效
    用于控制不同存储器类型的存储器控​​制器，并且当对错误类型执行访问操作时产生不可校正的错误故障

    公开(公告)号：US5884067A

    公开(公告)日：1999-03-16

    申请号：US549324

    申请日：1995-10-27

    申请人： Shawn Fontaine Storm ,  Bradley W. Hoffert ,  Mark A. Loomis

    发明人： Shawn Fontaine Storm ,  Bradley W. Hoffert ,  Mark A. Loomis

    IPC分类号： G09G5/39 ,  G06F3/14

    CPC分类号： G06F13/1694 ,  G09G5/39

    摘要： A memory controller method and apparatus wherein data to be written to a memory device is stored in a data queue, the data queue has a plurality of entries wherein at least two of the entries are combined to store a single datum, the single datum is wider than a single entry of the entries and addresses associated with the stored data of the data queue are stored in an address queue, thereby providing a circular write buffer. Specific memory modules of a plurality of memory modules to be refreshed are indicated to a refresh controller to thereby selectively control which of the memory modules are refreshed by the refresh controller. Access is controlled to the plurality of memory modules, each of the memory modules having an associated type. Configuration status information indicating the associated type for each of the memory modules is stored so that, if an access operation is performed to a wrong type, uncorrectable error faults are generated and can be detected. Planar data packing is performed by receiving a plurality of unpacked video data from the memory device, each of the unpacked video data having at least two channels of information, and packing the unpacked video data into packed video data by stripping at least one channel from each of the plurality of unpacked video data and then combining any remaining unstripped channel data, prior to sending the packed video data to a bus master. Planar data unpacking is performed by receiving the packed video data from the bus master, the packed video data having at least one missing channel of the at least two channels of the unpacked video data, and then expanding the packed video data to unpacked video data for storage in the memory device, thereby providing video data translation.

    摘要翻译： 一种存储器控制器方法和装置，其中要写入存储器件的数据被存储在数据队列中，数据队列具有多个条目，其中至少两个条目被组合以存储单个数据，单个数据较宽 比与数据队列的存储数据相关联的条目和地址的单个条目存储在地址队列中，从而提供循环写入缓冲器。 要更新的多个存储器模块的特定存储器模块被指示给刷新控制器，从而选择性地控制刷新控制器刷新哪个存储器模块。 访问被控制到多个存储器模块，每个存储器模块具有相关联的类型。 存储指示每个存储器模块的相关联类型的配置状态信息，使得如果对错误类型执行访问操作，则生成不可校正的错误故障并且可以被检测。 通过从存储器设备接收多个未打包的视频数据来执行平面数据打包，每个解包的视频数据具有至少两个信道信道，并且通过从每个信道剥离至少一个信道将未打包的视频数据打包成打包的视频数据 的多个未打包的视频数据，然后在将打包的视频数据发送到总线主机之前组合任何剩余的未分离的通道数据。 通过从总线主机接收压缩的视频数据来执行平面数据解包，所述压缩视频数据具有至少两个未打包视频数据的通道的至少一个缺失通道，然后将打包的视频数据扩展到解包的视频数据， 存储在存储设备中，从而提供视频数据转换。

    Method and apparatus for clocking variable pixel frequencies and pixel depths in a memory display interface
    10.
    发明授权
    Method and apparatus for clocking variable pixel frequencies and pixel depths in a memory display interface 失效
    在存储器显示接口中对可变像素频率和像素深度进行计时的方法和装置

    公开(公告)号：US5502837A

    公开(公告)日：1996-03-26

    申请号：US928513

    申请日：1992-08-11

    申请人： Bradley W. Hoffert

    发明人： Bradley W. Hoffert

    IPC分类号： G06T1/60 ,  G06T11/00 ,  G09G5/18 ,  G09G5/395 ,  G09G1/28 ,  G06F1/04 ,  G06F1/12

    CPC分类号： G09G5/395 ,  G09G5/18

    摘要： A method and apparatus for synchronizing pixel data flow within a memory display interface (MDI) to enable variable pixel depths, and to support display devices requiring differing pixel rates. A clock circuit receives a pixel clock from a DAC, and generates a shift clock (VSCLK), a pipeline clock, and an input control signal, all of which are synchronized to the pixel clock. The pixel clock synchronizes color pixel data transfer from the MDI to the DAC. The pipeline clock synchronizes pixel data processing through a pixel processing pipeline according to the frequency of the pixel clock and the number of pixels processed in parallel through the pixel processing pipeline. The input control signal feeds the pixel data from a VRAM frame buffer into the pixel processing pipeline according to the pixel depth mode, the frequency of the pixel clock, and the number of pixels processed in parallel through the pixel processing pipeline. The VSCLK controls pixel data transfer from the VRAM frame buffer over the video bus according to the pixel depth mode and the frequency of the pixel clock.

    摘要翻译： 一种用于使存储器显示接口（MDI）内的像素数据流同步以实现可变像素深度并支持需要不同像素速率的显示设备的方法和装置。 时钟电路从DAC接收像素时钟，并产生与像素时钟同步的移位时钟（VSCLK），流水线时钟和输入控制信号。 像素时钟同步从MDI到DAC的彩色像素数据传输。 流水线时钟根据像素时钟的频率和通过像素处理流水线并行处理的像素的数量，通过像素处理流水线来同步像素数据处理。 输入控制信号根据像素深度模式，像素时钟的频率和通过像素处理流水线并行处理的像素的数量将来自VRAM帧缓冲器的像素数据馈送到像素处理流水线。 根据像素深度模式和像素时钟的频率，VSCLK通过视频总线控制来自VRAM帧缓冲器的像素数据传输。