公开(公告)号：US08816455B2

公开(公告)日：2014-08-26

申请号：US13657708

申请日：2012-10-22

Applicant: Crocus Technology, Inc.

Inventor： Neal Berger ,  Mourad El Baraji ,  Amitay Levi

IPC: H01L29/82

CPC classification number: H01L27/222 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/82 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract translation: 存储器件包括包括多个磁随机存取存储器（MRAM）单元的磁性层，第一导电层，包括连接多个MRAM单元中包括的MRAM单元的带的层和第二导电层。 第一导电层包括电连接到多个MRAM单元中的至少一个的导电部分，以及被配置为将数据写入多个MRAM单元中的至少一个的场线。 第二导电层包括电连接到多个MRAM单元中的至少一个MRAM单元的导电互连，其中磁性层设置在第一导电层和第二导电层之间。 多个MRAM单元中的至少一个直接附接到第二导电层和带。

公开(公告)号：US20130094283A1

公开(公告)日：2013-04-18

申请号：US13648221

申请日：2012-10-09

Applicant: CROCUS TECHNOLOGY, INC.

Inventor： Neal Berger ,  Jean-Pierre Nozieres ,  Virgile Javerliac

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C8/08 ,  G11C11/1659 ,  G11C11/1693

Abstract: A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity.

Abstract translation: 一种存储器件包括多个磁性随机存取存储器（MRAM）单元，一个场线，以及一个现场线控制器，被配置为产生穿过场线的写入序列。 写入序列用于将多位字写入多个MRAM单元。 多位字包括具有第一极性的位的第一子集和具有第二极性的位的第二子集。 所述写入顺序并行地写入与具有所述第一极性的所述第一第一子集对应的所述多个MRAM单元的至少一个子集，然后并行地写入所述多个MRAM单元的对应于具有 第二极性。

公开(公告)号：US20140195883A1

公开(公告)日：2014-07-10

申请号：US14207066

申请日：2014-03-12

Applicant: CROCUS TECHNOLOGY INC.

Inventor： Bertrand F. Cambou ,  Neal Berger ,  Mourad El Baraji

IPC: G06F11/08

CPC classification number: G06F11/08 ,  G06F7/02 ,  G06F2207/025 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C15/02 ,  G11C15/046

Abstract: A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.

Abstract translation: 检查引擎包括多个比较器，每个比较器包括对齐以存储包括在一组参考比特中的至少一个参考比特的第一方向特性，以及对准以呈现包括在一组目标比特中的至少一个目标比特的第二方向特性 。 多个比较器中的每一个被配置为基于第一方向特性和第二方向特性之间的相对对准来产生表示所述至少一个目标位和所述至少一个参考位之间的匹配水平的输出。 检查引擎被配置为使得多个比较器的输出被组合以产生组合输出。 检查引擎被配置为基于多个比较器的组合输出来确定目标比特的集合与参考比特集匹配。

公开(公告)号：US20140110802A1

公开(公告)日：2014-04-24

申请号：US13657708

申请日：2012-10-22

Applicant: CROCUS TECHNOLOGY, INC.,

Inventor： Neal Berger ,  Mourad El Baraji ,  Amitay Levi

IPC: H01L29/82

CPC classification number: H01L27/222 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/82 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract translation: 存储器件包括包括多个磁随机存取存储器（MRAM）单元的磁性层，第一导电层，包括连接多个MRAM单元中包括的MRAM单元的带的层和第二导电层。 第一导电层包括电连接到多个MRAM单元中的至少一个的导电部分，以及被配置为将数据写入多个MRAM单元中的至少一个的场线。 第二导电层包括电连接到多个MRAM单元中的至少一个MRAM单元的导电互连，其中磁性层设置在第一导电层和第二导电层之间。 多个MRAM单元中的至少一个直接附接到第二导电层和带。

公开(公告)号：US09054029B2

公开(公告)日：2015-06-09

申请号：US14468234

申请日：2014-08-25

Applicant: Crocus Technology Inc.

Inventor： Neal Berger ,  Mourad El Baraji ,  Amitay Levi

IPC: H01L27/22 ,  H01L29/82 ,  G11C11/16 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/222 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/82 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract translation: 存储器件包括包括多个磁随机存取存储器（MRAM）单元的磁性层，第一导电层，包括连接多个MRAM单元中包括的MRAM单元的带的层和第二导电层。 第一导电层包括电连接到多个MRAM单元中的至少一个的导电部分，以及被配置为将数据写入多个MRAM单元中的至少一个的场线。 第二导电层包括电连接到多个MRAM单元中的至少一个MRAM单元的导电互连，其中磁性层设置在第一导电层和第二导电层之间。 多个MRAM单元中的至少一个直接附接到第二导电层和带。

公开(公告)号：US20140361392A1

公开(公告)日：2014-12-11

申请号：US14468234

申请日：2014-08-25

Applicant: Crocus Technology Inc.

Inventor： Neal Berger ,  Mourad El Baraji ,  Amitay Levi

IPC: H01L27/22 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/222 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/82 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract translation: 存储器件包括包括多个磁随机存取存储器（MRAM）单元的磁性层，第一导电层，包括连接多个MRAM单元中包括的MRAM单元的带的层和第二导电层。 第一导电层包括电连接到多个MRAM单元中的至少一个的导电部分，以及被配置为将数据写入多个MRAM单元中的至少一个的场线。 第二导电层包括电连接到多个MRAM单元中的至少一个MRAM单元的导电互连，其中磁性层设置在第一导电层和第二导电层之间。 多个MRAM单元中的至少一个直接附接到第二导电层和带。

公开(公告)号：US08902643B2

公开(公告)日：2014-12-02

申请号：US13648221

申请日：2012-10-09

Applicant: Crocus Technology, Inc.

Inventor： Neal Berger ,  Jean-Pierre Nozieres ,  Virgile Javerliac

IPC: G11C11/00 ,  G11C8/08 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G11C8/08 ,  G11C11/1659 ,  G11C11/1693

Abstract: A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity.

Abstract translation: 一种存储器件包括多个磁性随机存取存储器（MRAM）单元，一个场线，以及一个现场线控制器，被配置为产生穿过场线的写入序列。 写入序列用于将多位字写入多个MRAM单元。 多位字包括具有第一极性的位的第一子集和具有第二极性的位的第二子集。 所述写入顺序并行地写入与具有所述第一极性的所述第一第一子集对应的所述多个MRAM单元的至少一个子集，然后并行地写入所述多个MRAM单元的对应于具有 第二极性。