公开(公告)号：US20240339522A1

公开(公告)日：2024-10-10

申请号：US18292067

申请日：2022-12-01

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Chaoqi XU ,  Shuxian CHEN ,  Chunxia MA ,  Yi ZHANG ,  Penglong XU ,  Feng LIN ,  Ruibin CAO

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/66681 ,  H01L29/402 ,  H01L29/7816

Abstract: In a manufacturing method for an LDMOS integrated device, a provided semiconductor substrate has an NLDMOS area and a PLDMOS area; then a dielectric layer on the NLDMOS area and a dielectric layer on the PLDMOS area are formed on the semiconductor substrate, and a stress material layer is formed on the dielectric layer on the NLDMOS area and/or on the dielectric layer on the PLDMOS area, the thickness of the dielectric layer on the NLDMOS region being greater than the thickness of the dielectric layer on the PLDMOS region; then heat treatment is performed to adjust the stress of the stress material layer, so as to improve the electron mobility of a device; then the stress material layer is removed.

公开(公告)号：US20240222473A1

公开(公告)日：2024-07-04

申请号：US18684175

申请日：2022-12-20

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Feng LIN ,  Chaoqi XU ,  Shuxian CHEN ,  Chunxu LI ,  Li LU ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66734 ,  H01L21/2251 ,  H01L29/0619 ,  H01L29/41741 ,  H01L29/7813

Abstract: The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.

公开(公告)号：US20220384641A1

公开(公告)日：2022-12-01

申请号：US17886609

申请日：2022-08-12

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Huajun JIN ,  Guipeng SUN ,  Feng LIN ,  Shuxian CHEN

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/266

Abstract: A method for manufacturing a semiconductor device, and a semiconductor device. The method includes: providing a semiconductor substrate of a first conductivity type, forming a deep well of a second conductivity type in the semiconductor substrate, forming a channel region of the first conductivity type, a first well region of the first conductivity type, and a drift region of the second conductivity type in the deep well, the first well region and the channel region being spaced by a portion of the deep well, the drift region being located between the channel region and the first well region, forming an ion implantation region of the first conductivity type in the deep well, the ion implantation region being located under the drift region, and forming a source region of the second conductivity type and a drain region of the second conductivity type in the deep well.