公开(公告)号：US11979976B2

公开(公告)日：2024-05-07

申请号：US17383129

申请日：2021-07-22

Applicant: CelLink Corporation

Inventor： Kevin Michael Coakley ,  Malcolm Parker Brown ,  Dongao Yang ,  Michael Lawrence Miller ,  Paul Henry Lego

IPC: H05K3/20 ,  H01M50/519 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/06 ,  H05K3/28 ,  H05K3/46 ,  H05K3/04 ,  H05K3/44

CPC classification number: H05K1/0201 ,  H01M50/519 ,  H05K1/118 ,  H05K3/007 ,  H05K3/0073 ,  H05K3/06 ,  H05K3/20 ,  H05K3/281 ,  H05K3/4623 ,  H05K3/046 ,  H05K3/064 ,  H05K3/44 ,  H05K3/445 ,  Y02E60/10

Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.

公开(公告)号：US20240276632A1

公开(公告)日：2024-08-15

申请号：US18625063

申请日：2024-04-02

Applicant: CelLink Corporation

Inventor： Kevin Michael Coakley ,  Malcolm Parker Brown ,  Dongao Yang ,  Michael Lawrence Miller ,  Paul Henry Lego

IPC: H05K1/02 ,  H01M50/519 ,  H05K1/11 ,  H05K3/00 ,  H05K3/04 ,  H05K3/06 ,  H05K3/20 ,  H05K3/28 ,  H05K3/44 ,  H05K3/46

CPC classification number: H05K1/0201 ,  H01M50/519 ,  H05K1/118 ,  H05K3/007 ,  H05K3/0073 ,  H05K3/06 ,  H05K3/20 ,  H05K3/281 ,  H05K3/4623 ,  H05K3/046 ,  H05K3/064 ,  H05K3/44 ,  H05K3/445 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/10037 ,  H05K2203/066 ,  Y02E60/10 ,  Y10T29/49156

Abstract: A method of forming a flexible interconnect circuit is described. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.

公开(公告)号：US12035459B2

公开(公告)日：2024-07-09

申请号：US18521587

申请日：2023-11-28

Applicant: CelLink Corporation

Inventor： Kevin Michael Coakley ,  Malcolm Parker Brown ,  Dongao Yang ,  Michael Lawrence Miller ,  Paul Henry Lego

IPC: H05K3/00 ,  H01M50/519 ,  H05K1/02 ,  H05K1/11 ,  H05K3/06 ,  H05K3/20 ,  H05K3/28 ,  H05K3/46

CPC classification number: H05K1/0201 ,  H01M50/519 ,  H05K1/118 ,  H05K3/007 ,  H05K3/0073 ,  H05K3/06 ,  H05K3/20 ,  H05K3/281 ,  H05K3/4623 ,  H05K3/064 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/10037 ,  H05K2203/066 ,  Y02E60/10 ,  Y10T29/49156

Abstract: A method of forming a flexible interconnect circuit is described. The method may comprise laminating a substrate to a conductive layer and patterning the conductive layer using a laser while the conductive layer remains laminated to the substrate thereby forming a first conductive portion and a second conductive portion of the conductive layer. The substrate maintains the orientation of the first conductive portion relative to the second conductive portion during and after patterning. The method may also comprise laminating a first insulator to the conductive layer and removing the substrate from the conductive layer such that the first insulator maintains the orientation of the first conductive portion relative to the second conductive portion while and after the substrate is removed. The method may also comprise laminating a second insulator to the second side of the conductive layer while the first insulator remains laminated to the substrate.

公开(公告)号：US11116070B2

公开(公告)日：2021-09-07

申请号：US16034899

申请日：2018-07-13

Applicant: CelLink Corporation

Inventor： Kevin Michael Coakley ,  Malcolm Parker Brown ,  Dongao Yang ,  Michael Lawrence Miller ,  Paul Henry Lego

IPC: H05K3/20 ,  H05K3/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/28 ,  H05K3/06

Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.

公开(公告)号：US20240098873A1

公开(公告)日：2024-03-21

申请号：US18521587

申请日：2023-11-28

Applicant: CelLink Corporation

Inventor： Kevin Michael Coakley ,  Malcom Parker Brown ,  Dongao Yang ,  Michael Lawrence Miller ,  Paul Henry Lego

IPC: H05K1/02 ,  H01M50/519 ,  H05K1/11 ,  H05K3/00 ,  H05K3/06 ,  H05K3/20 ,  H05K3/28 ,  H05K3/46

CPC classification number: H05K1/0201 ,  H01M50/519 ,  H05K1/118 ,  H05K3/007 ,  H05K3/0073 ,  H05K3/06 ,  H05K3/20 ,  H05K3/281 ,  H05K3/4623 ,  H05K3/064 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/10037 ,  Y02E60/10

Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.

公开(公告)号：US20210352798A1

公开(公告)日：2021-11-11

申请号：US17383129

申请日：2021-07-22

Applicant: CelLink Corporation

Inventor： Kevin Michael Coakley ,  Malcolm Parker Brown ,  Dongao Yang ,  Michael Lawrence Miller ,  Paul Henry Lego

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/20 ,  H05K3/28 ,  H05K3/06

Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.

公开(公告)号：US20190021161A1

公开(公告)日：2019-01-17

申请号：US16034899

申请日：2018-07-13

Applicant: CelLink Corporation

Inventor： Kevin Michael Coakley ,  Malcolm Parker Brown ,  Dongao Yang ,  Michael Lawrence Miller ,  Paul Henry Lego

IPC: H05K1/02 ,  H05K3/00

Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.