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    DISPLAY SUBSTRATE, MANFFACTURING METHOD THEREOF, AND DISPLAY DEVICE
    4.
    发明公开
    DISPLAY SUBSTRATE, MANFFACTURING METHOD THEREOF, AND DISPLAY DEVICE 审中-公开

    公开(公告)号：US20230345798A1

    公开(公告)日：2023-10-26

    申请号：US17636147

    申请日：2021-04-25

    申请人： Chengdu BOE Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

    发明人： Hongguang YUAN ,  Xiaoliang GUO ,  Zhongfei DONG ,  Zhilong YUAN ,  Donghua JIANG ,  Guobo YANG

    IPC分类号： H10K59/80 ,  H10K59/131 ,  H10K59/12

    CPC分类号： H10K59/873 ,  H10K59/131 ,  H10K59/1201

    摘要： A display substrate includes a display region, and the display region includes an open pore region, a first pixel region and an isolation region; the isolation region is located between the first pixel region and the open pore region, the isolation region surrounds the open pore region, and a boundary line between the open pore region and the isolation region is a cutting line; the display substrate further includes: a fracture barrier structure, a peel-off barrier structure and an encapsulation structure, the fracture barrier structure being located in an isolation region, the isolation region including a reserved cutting transition region located between the fracture barrier structure and the open pore region; a peel-off barrier structure being located in the reserved cutting transition region; the distance L between the side of the peel-off barrier structure closest to the open pore region and the cutting line being such that: 0 μm≤L≤30 μm; a first portion of the encapsulation structure being located on a side of the peel-off barrier structure facing away from the base; and the peel-off barrier structure making the surface of the display substrate in contact with the first portion uneven.

    DISPLAY SUBSTRATE AND DISPLAY DEVICE THEREOF
    8.
    发明申请
    DISPLAY SUBSTRATE AND DISPLAY DEVICE THEREOF 有权

    公开(公告)号：US20230050620A1

    公开(公告)日：2023-02-16

    申请号：US17789948

    申请日：2021-08-05

    申请人： CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

    发明人： Liang SONG ,  Jiahao XU ,  Dongliang LU ,  Fei LIAO ,  Donghua JIANG ,  Guobo YANG ,  Pengyu LIAO ,  Wuyang ZHAO

    IPC分类号： H01L27/32

    摘要： The present disclosure relates to a display substrate and a display device thereof. The display substrate comprises: a substrate; a first wiring extending in a first direction on the substrate; a first dielectric layer on the substrate and the first wiring; a second wiring extending in the first direction on the first dielectric layer, wherein an orthographic projection of the second wiring on the substrate at least partially overlaps with an orthographic projection of the first wiring on the substrate; a conformal dielectric layer on the first dielectric layer and the second wiring; a third wiring and a fourth wiring disposed at spacings in the first direction on the conformal dielectric layer, wherein orthographic projections of the third wiring and the fourth wiring on the substrate at least partially overlap with the orthographic projections of the first wiring and the second wiring on the substrate.

    VIA-HOLE ETCHING METHOD
    10.
    发明申请
    VIA-HOLE ETCHING METHOD 有权
    通孔蚀刻方法

    公开(公告)号：US20150303099A1

    公开(公告)日：2015-10-22

    申请号：US14361083

    申请日：2013-12-03

    申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  CHENGDU BOE OPTOELETRONICS TECHNOLOGY CO., LTD.

    发明人： Byung Chun LEE ,  Donghua JIANG ,  Yongyi FU ,  Wuyang ZHAO ,  Chundong LI

    IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L21/311

    CPC分类号： H01L21/76804 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76895

    摘要： The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.

    摘要翻译： 本发明公开了一种与半导体制造领域相关的通孔蚀刻方法，该方法克服了以往的通孔蚀刻方法中的通孔的不可控端点和不利的形状角的缺陷。 通孔蚀刻方法包括：形成用于通孔蚀刻的结构，包括：顺序地形成在基板上的低温多晶硅层，栅极绝缘层，栅极金属层和层间绝缘层 ; 在所述用于通孔蚀刻的结构上形成包括通孔掩模图案的掩模层; 通过使用第一蚀刻工艺，将用于通孔蚀刻的结构蚀刻到栅极绝缘层的第一厚度; 通过使用第二蚀刻工艺，蚀刻用于通孔蚀刻的结构以蚀刻掉栅极绝缘层的剩余厚度，并露出低温多晶硅层; 去除掩模层以形成通孔结构。