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    Method of manufacturing a non-volatile memory device
    1.
    发明申请
    Method of manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US20070037328A1

    公开(公告)日：2007-02-15

    申请号：US11203087

    申请日：2005-08-15

    Applicant: Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    Inventor： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC: H01L21/84 ,  H01L21/00

    CPC classification number: H01L27/115 ,  H01L27/11568

    Abstract: A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

    Abstract translation: 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

    Non-volatile memory cells and methods of manufacturing the same
    3.
    发明授权
    Non-volatile memory cells and methods of manufacturing the same 有权
    非易失性存储单元及其制造方法

    公开(公告)号：US07468299B2

    公开(公告)日：2008-12-23

    申请号：US11197659

    申请日：2005-08-04

    Applicant: ChiaHua Ho ,  Erh-Kun Lai ,  Hang-Ting Lue

    Inventor： ChiaHua Ho ,  Erh-Kun Lai ,  Hang-Ting Lue

    IPC: H01L21/336

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: Methods for forming non-volatile memory cells include: (a) providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least two source/drain regions are separated by a recess trench having an exposed surface, wherein the trench extends downward into the substrate to a depth position below the at least two source/drain regions; (b) forming a charge-trapping layer on the exposed surfaces of the dielectric material and the recess trench; and (c) forming a gate above the charge-trapping layer.

    Abstract translation: 用于形成非易失性存储单元的方法包括：（a）提供具有至少两个源极/漏极区域的半导体衬底和设置在至少两个源极/漏极区域中的至少一个的衬底上的电介质材料，其中电介质 材料具有暴露的表面，并且其中所述至少两个源极/漏极区域被具有暴露表面的凹槽分隔开，其中所述沟槽向下延伸到所述衬底中至所述至少两个源极/漏极区域下方的深度位置; （b）在电介质材料和凹槽沟的暴露表面上形成电荷捕获层; 和（c）在电荷俘获层上形成栅极。

    Method of manufacturing a non-volatile memory device
    4.
    发明授权
    Method of manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US07414282B2

    公开(公告)日：2008-08-19

    申请号：US11203087

    申请日：2005-08-15

    Applicant: Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    Inventor： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC: H01L29/76

    CPC classification number: H01L27/115 ,  H01L27/11568

    Abstract: A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

    Abstract translation: 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅极上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

    Dual gate multi-bit semiconductor memory array
    5.
    发明申请
    Dual gate multi-bit semiconductor memory array 有权
    双门多位半导体存储器阵列

    公开(公告)号：US20070194365A1

    公开(公告)日：2007-08-23

    申请号：US11356659

    申请日：2006-02-17

    Applicant: ChiaHua Ho ,  Hang-Ting Lue

    Inventor： ChiaHua Ho ,  Hang-Ting Lue

    IPC: H01L29/76

    CPC classification number: H01L27/115 ,  H01L27/11568

    Abstract: An array of memory cells is arranged in columns and one or more rows on a semiconductor substrate. Each cell has a source, a drain, a first gate and a second gate. The array includes a plurality of gate control lines, each of which corresponds to one of the columns of the memory cells, where each control line connects to the first gate of the memory cell in the corresponding column in each of the rows; and one or more word lines, each of which corresponds to one of the rows of the memory cells, where each word line connects to the second gate of each of the cells in the corresponding row.

    Abstract translation: 存储单元阵列布置成半导体衬底上的一列或多行。 每个单元具有源极，漏极，第一栅极和第二栅极。 阵列包括多个栅极控制线，每条栅极控制线对应于存储器单元的列之一，其中每个控制线连接到每行的相应列中的存储单元的第一栅极; 以及一个或多个字线，每个字线对应于存储器单元的行之一，其中每个字线连接到相应行中每个单元的第二个栅极。

    Dual gate multi-bit semiconductor memory array
    6.
    发明授权
    Dual gate multi-bit semiconductor memory array 有权
    双门多位半导体存储器阵列

    公开(公告)号：US07902589B2

    公开(公告)日：2011-03-08

    申请号：US11356659

    申请日：2006-02-17

    Applicant: ChiaHua Ho ,  Hang-Ting Lue

    Inventor： ChiaHua Ho ,  Hang-Ting Lue

    IPC: H01L29/792

    CPC classification number: H01L27/115 ,  H01L27/11568

    Abstract: An array of memory cells is arranged in columns and one or more rows on a semiconductor substrate. Each cell has a source, a drain, a first gate and a second gate. The array includes a plurality of gate control lines, each of which corresponds to one of the columns of the memory cells, where each control line connects to the first gate of the memory cell in the corresponding column in each of the rows; and one or more word lines, each of which corresponds to one of the rows of the memory cells, where each word line connects to the second gate of each of the cells in the corresponding row.

    Abstract translation: 存储单元阵列布置成半导体衬底上的一列或多行。 每个单元具有源极，漏极，第一栅极和第二栅极。 阵列包括多个栅极控制线，每条栅极控制线对应于存储器单元的列之一，其中每个控制线连接到每行的相应列中的存储单元的第一栅极; 以及一个或多个字线，每个字线对应于存储器单元的行之一，其中每个字线连接到相应行中每个单元的第二个栅极。

    Method of manufacturing a non-volatile memory device
    7.
    发明申请
    Method of manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US20090075466A1

    公开(公告)日：2009-03-19

    申请号：US12216679

    申请日：2008-07-09

    Applicant: Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    Inventor： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC: H01L21/3205

    CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115

    Abstract: A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

    Abstract translation: 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅极上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

    Non-volatile memory cells and methods of manufacturing the same
    9.
    发明申请
    Non-volatile memory cells and methods of manufacturing the same 有权
    非易失性存储单元及其制造方法

    公开(公告)号：US20070031999A1

    公开(公告)日：2007-02-08

    申请号：US11197659

    申请日：2005-08-04

    Applicant: ChiaHua Ho ,  Erh-Kun Lai ,  Hang-Ting Lue

    Inventor： ChiaHua Ho ,  Erh-Kun Lai ,  Hang-Ting Lue

    IPC: H01L21/335 ,  H01L21/8232

    CPC classification number: H01L27/11568 ,  H01L27/115

    Abstract: Methods for forming non-volatile memory cells include: (a) providing a semiconductor substrate having at least two source/drain regions, and a dielectric material disposed on the substrate above at least one of the at least two source/drain regions wherein the dielectric material has an exposed surface, and wherein the at least two source/drain regions are separated by a recess trench having an exposed surface, wherein the trench extends downward into the substrate to a depth position below the at least two source/drain regions; (b) forming a charge-trapping layer on the exposed surfaces of the dielectric material and the recess trench; and (c) forming a gate above the charge-trapping layer.

    Abstract translation: 用于形成非易失性存储单元的方法包括：（a）提供具有至少两个源极/漏极区域的半导体衬底和设置在至少两个源极/漏极区域中的至少一个的衬底上的电介质材料，其中电介质 材料具有暴露的表面，并且其中所述至少两个源极/漏极区域被具有暴露表面的凹槽分隔开，其中所述沟槽向下延伸到所述衬底中至所述至少两个源极/漏极区域下方的深度位置; （b）在电介质材料和凹槽沟的暴露表面上形成电荷捕获层; 和（c）在电荷俘获层上形成栅极。

    Dual gate multi-bit semiconductor memory
    10.
    发明授权
    Dual gate multi-bit semiconductor memory 有权
    双门多位半导体存储器

    公开(公告)号：US07130221B1

    公开(公告)日：2006-10-31

    申请号：US11234983

    申请日：2005-09-26

    Applicant: ChiaHua Ho ,  Hang-Ting Lue

    Inventor： ChiaHua Ho ,  Hang-Ting Lue

    IPC: G11C11/34

    CPC classification number: G11C16/0475 ,  G11C11/5671

    Abstract: A method for altering and reading the contents of a memory cell includes the steps of: applying programming voltages to a first control gate and to a second control gate to cause carriers to be injected and trapped in either a first charge trapping region or in a second charge trapping region; applying erasing voltages to the first control gate and to the second control gate to cause the trapped carriers to be removed from the first charge trapping region and/or the second charge trapping region; and applying a sequence of reading voltages to the first control gate and to the second control gate for determining a state of each of the first and the second charge trapping regions.

    Abstract translation: 一种用于改变和读取存储单元的内容的方法包括以下步骤：将编程电压施加到第一控制栅极和第二控制栅极，以使载流子注入并俘获在第一电荷捕获区域或第二电荷俘获区域中 电荷捕获区; 对第一控制栅极和第二控制栅极施加擦除电压，以使捕获的载流子从第一电荷俘获区域和/或第二电荷俘获区域移除; 以及向所述第一控制栅极和所述第二控制栅极施加读取电压的序列，以确定所述第一和第二电荷俘获区域中的每一个的状态。

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