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    Method of manufacturing a non-volatile memory device
    1.
    发明申请
    Method of manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US20070037328A1

    公开(公告)日：2007-02-15

    申请号：US11203087

    申请日：2005-08-15

    申请人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

    摘要翻译： 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

    Method of manufacturing a non-volatile memory device
    3.
    发明授权
    Method of manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US07414282B2

    公开(公告)日：2008-08-19

    申请号：US11203087

    申请日：2005-08-15

    申请人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L29/76

    CPC分类号： H01L27/115 ,  H01L27/11568

    摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

    摘要翻译： 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅极上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

    Method of manufacturing a non-volatile memory device
    4.
    发明申请
    Method of manufacturing a non-volatile memory device 有权
    制造非易失性存储器件的方法

    公开(公告)号：US20090075466A1

    公开(公告)日：2009-03-19

    申请号：US12216679

    申请日：2008-07-09

    申请人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： Chiahua Ho ,  Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L21/3205

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115

    摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.

    摘要翻译： 一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。 低字线电阻由存储器件的主栅极上的金属硅化物层形成。 在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

    Method of forming bottom oxide for nitride flash memory
    5.
    发明授权
    Method of forming bottom oxide for nitride flash memory 有权
    形成氮化物闪存底部氧化物的方法

    公开(公告)号：US08846549B2

    公开(公告)日：2014-09-30

    申请号：US11235786

    申请日：2005-09-27

    申请人： Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L21/31 ,  G11C16/04 ,  H01L21/28 ,  H01L29/51

    CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/513

    摘要： A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19 cm−3 and an interface trap density of up to 5E11 cm−2 eV−1. The three-layer structure may be a charge-trapping structure for the memory device, and the memory device may further include a gate over the structure and source and drain regions in the substrate.

    摘要翻译： 半导体衬底上的非易失性存储器件可以包括衬底上的底部氧化物层，底部氧化物层上的中间氮化硅层和中间层上的顶部氧化物层。 底部氧化物层可以具有高达5E19cm-3的氢浓度和高达5E11cm-2eV-1的界面陷阱密度。 三层结构可以是用于存储器件的电荷捕获结构，并且存储器件还可以包括在结构上的栅极和衬底中的源极和漏极区域。

    Asymmetric floating gate NAND flash memory
    6.
    发明授权
    Asymmetric floating gate NAND flash memory 有权
    非对称浮栅NAND闪存

    公开(公告)号：US07560762B2

    公开(公告)日：2009-07-14

    申请号：US11209437

    申请日：2005-08-23

    申请人： Yen-Hao Shih ,  Chia-Hua Ho ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： Yen-Hao Shih ,  Chia-Hua Ho ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L29/80

    CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521

    摘要： A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate (i.e., wordline) bias voltage will couple the floating gate with a voltage which can invert the channel under the floating gate. The inversion channel under the floating gate can thus serve as the source/drain. As a result, the memory device does not need a shallow junction, or an assist-gate. In addition, the memory device exhibits relatively low floating gate-to-floating gate (FG-FG) interference.

    摘要翻译： NAND型闪存器件包括覆盖相应字线的非对称浮动栅极。 给定的浮动栅极被充分地耦合到其相应的字线，使得大的栅极（即，字线）偏置电压将使浮动栅极与可以反转浮动栅极下方的沟道的电压耦合。 因此，浮置栅极下的反相通道可以作为源极/漏极。 结果，存储器件不需要浅结或辅助栅。 此外，存储器件具有相对较低的浮置栅极至浮置栅极（FG-FG）干扰。

    SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE
    8.
    发明申请
    SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE 有权
    具有改进位线电容的半导体结构

    公开(公告)号：US20140054535A1

    公开(公告)日：2014-02-27

    申请号：US13594353

    申请日：2012-08-24

    申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    IPC分类号： H01L47/00

    CPC分类号： H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

    摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

    摘要翻译： 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。

    Dual-gate, sonos, non-volatile memory cells and arrays thereof
    9.
    发明授权
    Dual-gate, sonos, non-volatile memory cells and arrays thereof 有权
    双栅极，超声波，非易失性存储单元及其阵列

    公开(公告)号：US07973366B2

    公开(公告)日：2011-07-05

    申请号：US11352788

    申请日：2006-02-13

    申请人： Chia-Hua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    发明人： Chia-Hua Ho ,  Hang-Ting Lue ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7923 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

    摘要： Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trapping structure and proximate to the source region; and a second gate disposed above the charge-trapping structure and proximate to the drain region; where the first gate and the second gate are separated by a first nanospace are provided, along with arrays including a plurality of such cells, methods of manufacturing such cells and methods of operating such cells.

    摘要翻译： 存储单元，其包括具有由沟道区域分离的源极区域和漏极区域的半导体衬底; 电荷捕获结构，设置在所述半导体衬底的沟道区之上; 设置在电荷捕获结构上方并靠近源极区的第一栅极; 以及第二栅极，其设置在所述电荷捕获结构的上方并且靠近所述漏极区; 提供了第一栅极和第二栅极被第一纳米级分隔开的区域，以及包括多个这样的电池的阵列，制造这种电池的方法以及操作这种电池的方法。

    Semiconductor structure with improved capacitance of bit line
    10.
    发明授权
    Semiconductor structure with improved capacitance of bit line 有权
    具有改善位线电容的半导体结构

    公开(公告)号：US08704205B2

    公开(公告)日：2014-04-22

    申请号：US13594353

    申请日：2012-08-24

    申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

    IPC分类号： H01L47/00

    CPC分类号： H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

    摘要： A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

    摘要翻译： 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。