公开(公告)号：US08243494B2

公开(公告)日：2012-08-14

申请号：US12235773

申请日：2008-09-23

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh ,  Shih-Hung Chen

IPC分类号： G11C16/02 ,  H01L29/417

CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying the substrate body, a programmable resistive memory material overlying the first conductive material, a high selective material overlying the programmable resistive memory material, and a silicon nitride material overlying the high selective material. The high selective material in the pillar is isotropically etched on both sides of the high selective material to create a void on each side of the high selective material with a reduced length. A programmable resistive memory material is deposited in a confined area previously occupied by the reduced length of the poly, and the programmable resistive memory material is deposited into an area previously occupied by the silicon nitride material.

摘要翻译： 制造具有用于切换可编程电阻存储器中的相位变化的限定熔化区域的电阻器随机存取存储器的过程。 该工艺最初形成了一个支柱，该支柱包括衬底主体，覆盖衬底主体的第一导电材料，覆盖第一导电材料的可编程电阻性存储器材料，覆盖在可编程电阻性存储器材料上的高选择性材料， 选择性材料。 柱中的高选择性材料在高选择性材料的两侧进行各向同性蚀刻，以在长度较小的高选择性材料的每侧产生空隙。 可编程电阻式存储器材料沉积在先前由多晶硅长度减小的限制区域中，并且可编程电阻式存储器材料沉积到先前由氮化硅材料占据的区域中。

公开(公告)号：US08178405B2

公开(公告)日：2012-05-15

申请号：US12755897

申请日：2010-04-07

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/8242

CPC分类号： H01L45/122 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1683

摘要： A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode. Also, methods for making the memory cell device include steps of forming a bottom electrode island including an insulative element and a stop element over a bottom electrode, forming a separation layer surrounding the island, removing the stop element to form a hole over the insulative element in the separation layer, forming a conductive film in the hole and an insulative liner over conductive film, etching to form a cup-shaped conductive film having a rim and to form an opening through the insulative liner and the bottom of the cup-shaped conductive film to the surface of the bottom electrode, forming a plug of phase change memory material in the opening, and forming a top electrode in contact with the rim of the cup-shaped conductive film.

摘要翻译： 存储单元装置具有底部电极和顶部电极，与底部电极接触的存储器材料的插头以及具有接触顶部电极的边缘和接触存储器的底部开口的杯形导电构件 材料。 因此，存储单元中的导电路径从顶部电极通过导电杯状构件，并通过相变材料的塞子到达底部电极。 此外，用于制造存储单元器件的方法包括在底部电极上形成包括绝缘元件和止动元件的底部电极岛的步骤，形成围绕岛的分离层，去除止动元件以在绝缘元件上方形成孔 在分离层中，在孔中形成导电膜，在导电膜上形成绝缘衬垫，进行蚀刻以形成具有边缘的杯形导电膜，并且通过绝缘衬垫和杯状导电体的底部形成开口 在底部电极的表面形成薄膜，在开口中形成相变记忆材料塞，形成与杯状导电膜的边缘接触的顶部电极。

公开(公告)号：US08139393B2

公开(公告)日：2012-03-20

申请号：US12576212

申请日：2009-10-08

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  B82Y10/00 ,  G11C11/5664 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/122 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1633

摘要： A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A connective conductive layer joins the first and second memory layers and places the same in electrical contact. The structure is designed so that the first memory layer has a cross-sectional area less than that of the second memory layer.

摘要翻译： 可选择地显示第一和第二逻辑电平的存储器件。 第一导电材料具有形成在其上的第一存储层的第一表面，并且第二导电材料具有形成在其上的第二存储层的第二表面。 连接导电层连接第一和第二存储层并将其放置在电接触中。 该结构被设计成使得第一存储层的横截面积小于第二存储层的横截面面积。

公开(公告)号：US07972893B2

公开(公告)日：2011-07-05

申请号：US12469184

申请日：2009-05-20

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang-Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/00

CPC分类号： H01L45/1226 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

摘要： A method for making a memory device includes providing a dielectric material, having first and second upwardly and inwardly tapering surfaces and a surface segment connecting the first and second surfaces. First and second electrodes are formed over the first and second surfaces. A memory element is formed over the surface segment to electrically connect the first and second electrodes.

摘要翻译： 制造存储器件的方法包括提供具有第一和第二向上和向内渐缩的表面的电介质材料以及连接第一和第二表面的表面段。 第一和第二电极形成在第一和第二表面上。 存储元件形成在表面段上以电连接第一和第二电极。

公开(公告)号：US07923285B2

公开(公告)日：2011-04-12

申请号：US12351692

申请日：2009-01-09

申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

IPC分类号： H01L21/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1683

摘要： A non-volatile memory with a self-aligned RRAM element includes a lower electrode element, generally planar in form, having an inner contact surface; an upper electrode element, spaced from the lower electrode element; a containment structure extends between the upper electrode element and the lower electrode element, with a sidewall spacer element having a generally funnel-shaped central cavity with a central aperture; and a spandrel element positioned between the sidewall spacer element and the lower electrode. A RRAM element extends between the lower electrode element and the upper electrode, occupying at least a portion of the sidewall spacer element central cavity and projecting from the sidewall spacer terminal edge toward and making contact with the lower electrode. In this manner, the spandrel element inner surface is spaced from the RRAM element to define a thermal isolation cell adjacent the RRAM element.

摘要翻译： 具有自对准RRAM元件的非易失性存储器包括具有内接触表面的大体平面形状的下电极元件; 与所述下电极元件间隔开的上电极元件; 容纳结构在上电极元件和下电极元件之间延伸，侧壁间隔元件具有大致漏斗形的具有中心孔的中心腔; 以及位于侧壁间隔元件和下电极之间的突出元件。 RRAM元件在下电极元件和上电极之间延伸，占据侧壁间隔件元件中心腔的至少一部分并且从侧壁间隔件端子边缘朝向和与下电极接触。 以这种方式，伞形元件内表面与RRAM元件间隔开以限定与RRAM元件相邻的热隔离单元。

公开(公告)号：US07902589B2

公开(公告)日：2011-03-08

申请号：US11356659

申请日：2006-02-17

申请人： ChiaHua Ho ,  Hang-Ting Lue

发明人： ChiaHua Ho ,  Hang-Ting Lue

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： An array of memory cells is arranged in columns and one or more rows on a semiconductor substrate. Each cell has a source, a drain, a first gate and a second gate. The array includes a plurality of gate control lines, each of which corresponds to one of the columns of the memory cells, where each control line connects to the first gate of the memory cell in the corresponding column in each of the rows; and one or more word lines, each of which corresponds to one of the rows of the memory cells, where each word line connects to the second gate of each of the cells in the corresponding row.

摘要翻译： 存储单元阵列布置成半导体衬底上的一列或多行。 每个单元具有源极，漏极，第一栅极和第二栅极。 阵列包括多个栅极控制线，每条栅极控制线对应于存储器单元的列之一，其中每个控制线连接到每行的相应列中的存储单元的第一栅极; 以及一个或多个字线，每个字线对应于存储器单元的行之一，其中每个字线连接到相应行中每个单元的第二个栅极。

公开(公告)号：US07741636B2

公开(公告)日：2010-06-22

申请号：US11457702

申请日：2006-07-14

申请人： ChiaHua Ho

发明人： ChiaHua Ho

IPC分类号： H01L29/18

CPC分类号： H01L27/24 ,  B82Y10/00 ,  H01L27/285 ,  H01L51/0047 ,  H01L51/0591

摘要： Integrated circuit nonvolatile memory uses programmable resistive elements. In some examples, conductive structures such as electrodes are prepared, and the programmable resistive elements are laid upon the prepared electrodes. This prevents contamination of the programmable resistive elements from previous fabrication steps.

摘要翻译： 集成电路非易失性存储器使用可编程电阻元件。 在一些示例中，制备诸如电极的导电结构，并且将可编程电阻元件放置在所制备的电极上。 这防止可编程电阻元件受到先前制造步骤的污染。

公开(公告)号：US20100105165A1

公开(公告)日：2010-04-29

申请号：US12683007

申请日：2010-01-06

申请人： ChiaHua HO ,  Erh-Kun Lai

发明人： ChiaHua HO ,  Erh-Kun Lai

IPC分类号： H01L21/34

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1633

摘要： The present invention provides multilevel-cell memory structures with multiple memory layer structures where each memory layer structure includes a tungsten oxide region that defines different read current levels for a plurality of logic states. Each memory layer structure can provide two bits of information, which constitutes four logic states, by the use of the tungsten oxide region that provides multilevel-cell function in which the four logic states equate to four different read current levels. A memory structure with two memory layer structures would provide four bits of storage sites and 16 logic states. In one embodiment, each of the first and second memory layer structures includes a tungsten oxide region extending into a principle surface of a tungsten plug member where the outer surface of the tungsten plug is surrounded by a barrier member.

摘要翻译： 本发明提供具有多个存储层结构的多电平单元存储器结构，其中每个存储层结构包括为多个逻辑状态定义不同读取电流电平的氧化钨区域。 每个存储器层结构可以通过使用提供多电平单元功能的氧化钨区域来提供构成四个逻辑状态的两位信息，其中四个逻辑状态等于四个不同的读取电流电平。 具有两个存储器层结构的存储器结构将提供四位存储位置和16个逻辑状态。 在一个实施例中，第一和第二存储层结构中的每一个包括延伸到钨插塞构件的主表面中的钨氧化物区域，其中钨插塞的外表面被阻挡构件包围。

公开(公告)号：US07605079B2

公开(公告)日：2009-10-20

申请号：US11382799

申请日：2006-05-11

申请人： Erh Kun Lai ,  Chiahua Ho ,  Yi Chou Chen ,  Kuang Yeu Hsieh

发明人： Erh Kun Lai ,  Chiahua Ho ,  Yi Chou Chen ,  Kuang Yeu Hsieh

IPC分类号： H01L21/44

CPC分类号： H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/14 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： A method for manufacturing a phase change memory device comprises forming an electrode layer. Electrodes are made in the electrode layer using conductor fill techniques that are also used inter-layer conductors for metallization layers, in order to improve process scaling with shrinking critical dimensions for metallization layers. The electrode layer is made by forming a multi-layer dielectric layer on a substrate, etching the multi-layer dielectric layer to form vias for electrode members contacting circuitry below, forming insulating spacers on the vias, etching through a top layer in the multi-layer dielectric layer to form trenches between the insulating spacers for electrode members contacting circuitry above, filling the vias and trenches with a conductive material using the metallization process. Thin film bridges of memory material are formed over the electrode layer.

摘要翻译： 一种相变存储器件的制造方法，包括形成电极层。 使用导体填充技术在电极层中制造电极，该技术也用于金属化层的层间导体，以便通过金属化层的缩小临界尺寸改善工艺规模。 电极层是通过在衬底上形成多层电介质层而形成的，蚀刻多层电介质层以形成接触下面电路的电极构件的通路，在通孔上形成绝缘隔离层， 以在用于接触上述电路的电极部件的绝缘间隔物之间​​形成沟槽，用导电材料使用金属化工艺填充过孔和沟槽。 存储材料的薄膜桥形成在电极层上。

公开(公告)号：US07599217B2

公开(公告)日：2009-10-06

申请号：US11357902

申请日：2006-02-17

申请人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Yeu Hsieh

发明人： Erh-Kun Lai ,  Chiahua Ho ,  Kuang Yeu Hsieh

IPC分类号： G11C11/00

CPC分类号： H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1691

摘要： A memory cell device, having a memory material switchable between electrical property states by the application of energy, comprises an electrode, a separation layer against an electrode surface, a hole in the separation layer, a second material in the hole defining a void having a downwardly and inwardly tapering void region. A memory material is in the void region in electrical contact with the electrode surface. A second electrode is in electrical contact with the memory material. Energy passing between the first and second electrodes is concentrated within the memory material so to facilitate changing an electrical property state of the memory material. The memory material may comprise a phase change material. The second material may comprise a high density plasma-deposited material. A method for making a memory cell device is also discussed.

摘要翻译： 具有可通过施加能量在电性能状态之间切换的记忆材料的存储单元装置包括电极，与电极表面相对的分离层，分离层中的孔，孔中的第二材料限定具有 向下和向内逐渐变细的空隙区域。 记忆材料位于与电极表面电接触的空隙区域中。 第二电极与记忆材料电接触。 在第一和第二电极之间的能量通过集中在存储材料内，以便于改变存储材料的电性能状态。 记忆材料可以包括相变材料。 第二材料可以包括高密度等离子体沉积材料。 还讨论了制造存储单元器件的方法。