公开(公告)号：US09258001B1

公开(公告)日：2016-02-09

申请号：US14016972

申请日：2013-09-03

Applicant: Cirrus Logic, Inc.

Inventor： Tejasvi Das ,  Alvin C. Storvik

IPC: H03L7/087 ,  H03L7/093 ,  H03L7/14 ,  H03L7/10 ,  H03L7/107

CPC classification number: H03L7/148 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/103 ,  H03L7/105 ,  H03L7/1075 ,  H03L7/146 ,  H03L7/18 ,  H03L7/22 ,  H03L2207/06

Abstract: An oscillator of a phase-locked loop (PLL) or frequency-locked loop (FLL) may include two inputs. The two inputs may include a first analog input and a second digital input. The second digital input may receive a digital signal setting a desired output clock frequency of the oscillator and/or indicating an approximate frequency of frequency range for output by the oscillator. The first analog input may receive a voltage representative of a desired frequency for the output clock frequency of the PLL or FLL to fine-tune the output frequency from the approximate frequency set by the second digital input. The first analog input may be generated from a master clock input signal. When the master clock input signal disappears, the second digital signal controls the output frequency of the oscillator to allow redundant operation of the PLL or FLL even when no master clock input signal is present.

Abstract translation: 锁相环（PLL）或锁频环（FLL）的振荡器可以包括两个输入。 两个输入可以包括第一模拟输入和第二数字输入。 第二数字输入可以接收设置振荡器的期望输出时钟频率的数字信号和/或指示振荡器输出的频率范围的近似频率。 第一模拟输入可以接收代表PLL或FLL的输出时钟频率的期望频率的电压，以从由第二数字输入设置的近似频率微调输出频率。 第一模拟输入可以从主时钟输入信号产生。 当主时钟输入信号消失时，即使没有主时钟输入信号，第二数字信号控制振荡器的输出频率，以允许PLL或FLL的冗余操作。