利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

50 records (took 0.012 seconds)

    DLL calibration method for fast frequency change without re-locking
    1.
    发明授权
    DLL calibration method for fast frequency change without re-locking 有权

    公开(公告)号：US09716507B1

    公开(公告)日：2017-07-25

    申请号：US15098750

    申请日：2016-04-14

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Muhammad Nummer ,  Rob Abbott

    IPC: H03L7/10 ,  H03L7/099

    CPC classification number: H03L7/105 ,  H03L7/0805 ,  H03L7/0991 ,  H03L7/0995 ,  H03L7/183

    Abstract: A delay circuit includes a delay line configured to output an output signal by imposing a delay value on an input signal. The delay circuit further includes an arithmetic unit configured to calculate a control code for the delay value based on delay codes. The delay circuit further includes a delay locked loop (DLL) configured to generate the delay codes based on a clock signal. The delay circuit further includes a controller configured to suspend operation of the DLL when the clock signal operates at a first frequency, to set the DLL to operate based on a second frequency when the DLL is suspended, and to resume operation of the DLL when the clock signal operates at the second frequency without the need to relock the DLL.

    Smart lock-in circuit for phase-locked loops
    3.
    发明申请
    Smart lock-in circuit for phase-locked loops 有权
    用于锁相环的智能锁定电路

    公开(公告)号：US20060158261A1

    公开(公告)日：2006-07-20

    申请号：US11036837

    申请日：2005-01-15

    Applicant: Sangbeom Park

    Inventor： Sangbeom Park

    IPC: H03L7/00

    CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L7/105 ,  Y10S331/02

    Abstract: The smart lock-in circuits basically include a sensor, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensor, the output voltage of the sensor turns on the corresponding transistor, which provides a current to its output until the voltage at feedback reaches the midpoint voltage. The time to reach the midpoint voltage at a filter is simply equal to the charge stored at the filter divided by the current, which can be scaled by a device aspect ratio of the transistor. Consequently, all smart lock-in circuits provide an initial loop condition closer to the expected loop condition according to schedule.

    Abstract translation: 智能锁定电路基本上包括传感器，两个堆叠的PMOS晶体管，两个堆叠的NMOS晶体管和反馈线。 如果感测电压与传感器的中点电压相比没有达到预期的电压，则传感器的输出电压导通相应的晶体管，该晶体管向其输出提供电流，直到反馈电压达到中点电压。 到达滤波器的中点电压的时间简单地等于存储在滤波器中的电荷除以电流，其可以通过晶体管的器件长宽比来缩放。 因此，所有智能锁定电路根据时间表提供更接近预期环路条件的初始环路条件。

    Voltage controlled oscillator with automatic center frequency calibration
    4.
    发明授权
    Voltage controlled oscillator with automatic center frequency calibration 失效
    具有自动中心频率校准的压控振荡器

    公开(公告)号：US06556093B2

    公开(公告)日：2003-04-29

    申请号：US09950803

    申请日：2001-09-13

    Applicant: Jan Frans Lucien Craninckx ,  Mark Maria Albert Ingels ,  Frank Nico Lieven Op't Eynde ,  Joannes Mathilda Josephus Sevenhans

    Inventor： Jan Frans Lucien Craninckx ,  Mark Maria Albert Ingels ,  Frank Nico Lieven Op't Eynde ,  Joannes Mathilda Josephus Sevenhans

    IPC: H03B500

    CPC classification number: H03L7/099 ,  H03B2201/025 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/105

    Abstract: A voltage controlled oscillator with automatic center frequency calibration. The frequency range of the oscillator is increased by switchable capacitor circuits which add or remove extra capacitors in parallel with the variable capacitor of the resonant circuit. Different voltage versus frequency characteristics are obtained. The switchable capacitor circuits are controlled by a detection circuit that sends a reset pulse to a feedback circuit of the VCO when a control voltage from the feedback circuit reaches predetermined low or high voltage limits of the characteristics. Upon reception of the reset pulse, the feedback circuit changes the control voltage from the reached limit into an intermediate voltage between the low and high voltage limits. The control voltage is reset in the middle of a voltage versus frequency characteristic onto which the output frequency is also centered. The VCO includes a selection circuit adapted to immediately change the value of the control voltage.

    Abstract translation: 具有自动中心频率校准的压控振荡器。 振荡器的频率范围由可切换电容器电路增加，该电路与谐振电路的可变电容器并联地增加或除去额外的电容器。 获得不同的电压对频率特性。 可转换电容器电路由检测电路控制，当来自反馈电路的控制电压达到预定的特性的低或高电压极限时，检测电路向VCO的反馈电路发送复位脉冲。 在接收到复位脉冲时，反馈电路将控制电压从达到的极限改变为低电压极限和高电压极限之间的中间电压。 控制电压在输出频率也居中的电压对频率特性的中间被复位。 VCO包括适于立即改变控制电压的值的选择电路。

    System including phase lock loop circuit
    5.
    发明授权
    System including phase lock loop circuit 失效
    系统包括锁相环电路

    公开(公告)号：US6163186A

    公开(公告)日：2000-12-19

    申请号：US966786

    申请日：1997-11-10

    Applicant: Kozaburo Kurita

    Inventor： Kozaburo Kurita

    IPC: G06F1/10 ,  H03K3/0231 ,  H03K3/354 ,  H03L7/07 ,  H03L7/089 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03L7/06

    CPC classification number: G06F1/10 ,  H03K3/0231 ,  H03K3/354 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/10 ,  H03L7/105 ,  H03L7/18 ,  Y10S331/02

    Abstract: A PLL circuit includes a phase comparator which makes a comparison between an internal clock signal and a clock signal supplied from an external terminal, a charge pump circuit which produces a charging-up or discharging current in accordance with the output of the phase comparator, so as to drive a filter capacitor, a voltage-controlled oscillator the oscillation frequency of which is controlled by the held voltage of the filter capacitor, and a frequency divider circuit which generates the internal clock signal on the basis of the oscillation output of the voltage-controlled oscillator. The PLL circuit is additionally provided with a voltage detector circuit which detects whether the held voltage of the filter capacitor has been raised to a predetermined voltage or higher, and the function of forcibly lowering the held voltage of the filter capacitor down to a predetermined potential in accordance with the detection output of the voltage detector circuit. Besides, a system is provided with a detection and setting circuit which detects a state brought about by the electrical disconnection of the feedback loop of the PLL circuit, and which brings the PLL circuit into a predetermined state.

    Abstract translation: PLL电路包括相位比较器，用于比较内部时钟信号和从外部端子提供的时钟信号之间的比较，电荷泵电路根据相位比较器的输出产生充电或放电电流，因此 为了驱动滤波电容器，其振荡频率由滤波电容器的保持电压控制的压控振荡器，以及基于电压互感器的振荡输出产生内部时钟信号的分频器电路， 受控振荡器。 PLL电路另外设置有电压检测器电路，其检测滤波电容器的保持电压是否已经升高到预定电压或更高，并且将滤波电容器的保持电压强制降低到预定电位的功能 按照检测电路的检测输出。 此外，系统具有检测和设置电路，该检测和设置电路检测由PLL电路的反馈回路的电断开引起的状态，并且使PLL电路进入预定状态。

    PLL with lock up detector and lock acquisition circuit
    6.
    发明授权
    PLL with lock up detector and lock acquisition circuit 失效
    PLL带锁定检测器和锁定采集电路

    公开(公告)号：US4596963A

    公开(公告)日：1986-06-24

    申请号：US630406

    申请日：1984-07-13

    Applicant: Rodney J. Lawton ,  Peter W. Gaussen ,  Ian A. Strachan ,  Philip I. J. Ainsley

    Inventor： Rodney J. Lawton ,  Peter W. Gaussen ,  Ian A. Strachan ,  Philip I. J. Ainsley

    IPC: H03L7/18 ,  H03J7/28 ,  H03L7/089 ,  H03L7/10 ,  H03L7/12 ,  H03L7/06

    CPC classification number: H03L7/105 ,  H03L7/0891 ,  H03L7/12 ,  Y10S331/02

    Abstract: A phase lock loop circuit comprises a variable frequency oscillator having a control input and an output, a divider having an input coupled with the output of the oscillator and an output coupled with the first input of a phase or frequency comparator. The comparator has a second input for a reference frequency (F.sub.REF) and an output coupled with the oscillator control input for providing a signal which is related to the difference in phase or frequency of the signals at the first and second inputs to effect phase locking of the oscillator to the reference signal. A detector provides a switching signal when the control signal falls outside a predetermined range and a switch in the phase lock loop is responsive to the switching signal to open the loop.

    Abstract translation: 锁相环电路包括具有控制输入和输出的可变频率振荡器，具有与振荡器的输出耦合的输入的分频器和与相位或频率比较器的第一输入耦合的输出。 比较器具有用于参考频率（FREF）的第二输入和与振荡器控制输入耦合的输出，用于提供与第一和第二输入处的信号的相位或频率差相关的信号，以实现相位锁定 振荡器到参考信号。 当控制信号超出预定范围时，检测器提供切换信号，并且锁相环中的开关响应于切换信号以打开环路。

Patent Agency Ranking