公开(公告)号：US09633156B1

公开(公告)日：2017-04-25

申请号：US15047033

申请日：2016-02-18

Applicant: Cirrus Logic, Inc.

Inventor： Bhoodev Kumar ,  Saurabh Singh ,  Lei Zhu

IPC: H03K3/00 ,  G06F17/50

CPC classification number: G06F17/505 ,  G01R31/318541 ,  H03K3/012

Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.

公开(公告)号：US09300275B1

公开(公告)日：2016-03-29

申请号：US14339879

申请日：2014-07-24

Applicant: Cirrus Logic, Inc.

Inventor： Bhoodev Kumar ,  Saurabh Singh ,  Lei Zhu

IPC: H03K3/00 ,  H03K3/012 ,  G06F17/50

CPC classification number: G06F17/505 ,  G01R31/318541 ,  H03K3/012

Abstract: In accordance with embodiments of the present disclosure, a multi-bit pulsed latch circuit for an integrated circuit design system may include a pulse generator and a plurality of latches. The pulse generator may be configured to generate pulses. The plurality of latches may operate as storage elements and are coupled to the pulse generator in a manner so that the multi-bit pulsed latch circuit provides functionality of at least two flip flop elements, wherein the multi-bit pulsed latch circuit can replace the at least two flip flop elements that normally would be used by the integrated circuit design system.

Abstract translation: 根据本公开的实施例，用于集成电路设计系统的多位脉冲锁存电路可以包括脉冲发生器和多个锁存器。 脉冲发生器可以被配置为产生脉冲。 多个锁存器可以作为存储元件工作，并且以这样的方式耦合到脉冲发生器，使得多位脉冲锁存电路提供至少两个触发器元件的功能，其中多位脉冲锁存电路可以代替at 通常将由集成电路设计系统使用的至少两个触发器元件。

公开(公告)号：US09276594B2

公开(公告)日：2016-03-01

申请号：US13840345

申请日：2013-03-15

Applicant: Cirrus Logic, Inc.

Inventor： Cory Jay Peterson ,  Bhoodev Kumar ,  Daniel John Allen ,  Jeffrey D. Alderson

IPC: H03L7/06 ,  H03L7/10

CPC classification number: H03L7/104

Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.

Abstract translation: 当预期另一信号的变化时，通过延迟时间窗外的信号传播可以降低噪声。 可以在第一时钟信号的变化和第二时钟信号的变化之间定义时间窗口，在该时间窗口期间诸如数据信号的第三信号不传播通过电路。 当第一时钟信号在第一时钟信号处于与第二时钟信号不同的电平之后，第三信号发生变化时，第三信号改变的传播可被延迟直到接收到第二时钟信号的改变。 可以通过没有亚稳态的锁存和保持电路来实现延迟传播。

公开(公告)号：US20140266337A1

公开(公告)日：2014-09-18

申请号：US13840345

申请日：2013-03-15

Applicant: Cirrus Logic, Inc.

Inventor： Cory Jay Peterson ,  Bhoodev Kumar ,  Daniel John Allen ,  Jeffrey D. Alderson

IPC: H03L7/10

CPC classification number: H03L7/104

Abstract: Noise may be reduced by delaying signal propagation outside of a time window when a change in another signal is expected. A time window may be defined between the change of the first clock signal and the change of the second clock signal during which a third signal, such as a data signal, does not propagate through the circuit. When a change occurs in a third signal after the first clock signal change while the first clock signal is at a different level than a second clock signal, propagation of the third signal change may be delayed until a change in the second clock signal is received. Delayed propagation may be achieved through a latch and hold circuit with no metastability.

Abstract translation: 当预期另一信号的变化时，通过延迟时间窗外的信号传播可以降低噪声。 可以在第一时钟信号的变化和第二时钟信号的变化之间定义时间窗口，在该时间窗口期间诸如数据信号的第三信号不传播通过电路。 当第一时钟信号在第一时钟信号处于与第二时钟信号不同的电平之后，第三信号发生变化时，第三信号改变的传播可被延迟，直到接收到第二时钟信号的改变。 可以通过没有亚稳态的锁存和保持电路来实现延迟传播。